;;Established date:                  2006/03/01
;;********************************************************************
Clear_RAM:
	MOV	A,C_Ramaddress
	MOV	MP0,A
	MOV	A,C_Ramnumber
Clear_RAMLOOP:
	CLR	R0
	INC	MP0
	SDZ	ACC
	JMP	Clear_RAMLOOP
	RET
	
	
	
	
;;********************************************************************

INI_Timer:
INI_RAM:

        MOV     A,00000111B
        MOV     TMR0C,A



	MOV	A,C_TMR1C
	MOV	TMR1C,A
	MOV	A,00            ;C_TMR1L
	MOV	TMR1L,A
	MOV 	A,00            ;C_TMR1H
	MOV	TMR1H,A		;;If system clock is 12MHZ then each 34.66 microsecond polling rxd start bit one time.
	RET
	
	
	
;;********************************************************************
INI_PORT:
	CLR	PAC

        CLR     PA 


	SET     PAC.5
	
	NOP
	SET     PAC.6

	SET     PAC.7
	
	NOP
	
	SET	PBC
	
	SET	PDC
	CLR     PDC.0
	CLR     PDC.1

	CLR     PD.0
	CLR     PD.1

        NOP  	


        CH1_PWM_OFF
        CH2_PWM_OFF

	
	
	
	SET	PEC
	RET
;;********************************************************************







SBR_Delaysecond:
	MOV	A,4					
	MOV	M_TEMP2,A
	SET	M_TEMP1
	SET	ACC
L_Wait3s:
	CLR	WDT
	SNZ	F_Suspend		;about 1ms
	RET	
	SDZ	ACC
	JMP	L_Wait3s
	SDZ	M_TEMP1
	JMP	L_Wait3s		;260ms
	SDZ	M_TEMP2
	JMP	L_Wait3s
	RET
;;********************************************************************



SBR_Delay2us:
	MOV	A,08H
	SDZ	ACC
	JMP	$-1
	RET
;;********************************************************************