/* 
 * This GEL file (init6713.gel) is loaded on the command line 
 * of Code Composer. It provides example code on how to 
 * reset the C6x DSP and initialize the External Memory Interface.
 *
 */



/*
 * The StartUp() function is called every time you start
 * Code Composer.  You can customize this function to
 * initialize wait states in the EMIF or to perform 
 * other initialization.
 */
StartUp()
{
    /* C6713 specific memory mapping */
    GEL_MapOn();
    GEL_MapReset();

    GEL_MapAdd(0x00000000,0,0x00040000,1,1); /* Internal RAM (L2) */
    GEL_MapAdd(0x01800000,0,0x00000024,1,1); /* EMIF Control Registers */
    GEL_MapAdd(0x01844000,0,0x00000018,1,1); /* Cache Control Registers */
    GEL_MapAdd(0x01844020,0,0x00000008,1,1);
    GEL_MapAdd(0x01844030,0,0x00000008,1,1);
    GEL_MapAdd(0x01845000,0,0x00000008,1,1);
    GEL_MapAdd(0x01848200,0,0x00000010,1,1); /* CE0 Memory Attribute Registers */
    GEL_MapAdd(0x01848240,0,0x00000010,1,1); /* CE1 Memory Attribute Registers */
    GEL_MapAdd(0x01848280,0,0x00000010,1,1); /* CE2 Memory Attribute Registers */
    GEL_MapAdd(0x018482c0,0,0x00000010,1,1); /* CE3 Memory Attribute Registers */
    GEL_MapAdd(0x01860000,0,0x00000020,1,1); /* ROM Control Registers */
    GEL_MapAdd(0x018c0000,0,0x00000028,1,1); /* McBSP0 Registers */
    GEL_MapAdd(0x01900000,0,0x00000028,1,1); /* McBSP1 Registers */
    GEL_MapAdd(0x01940000,0,0x0000000c,1,1); /* Timer0 Registers */
    GEL_MapAdd(0x01980000,0,0x0000000c,1,1); /* Timer1 Registers */
    GEL_MapAdd(0x019c0000,0,0x0000000c,1,1); /* Interrupt Selector Regsters */
    GEL_MapAdd(0x01a00000,0,0x00000180,1,1); /* EDMA Parameter RAM */
    GEL_MapAdd(0x01a00600,0,0x00000200,1,1);
    GEL_MapAdd(0x01a0ffe0,0,0x00000020,1,1); /* EDMA Control Registers */ 
    GEL_MapAdd(0x01b4c000,0,0x00000024,1,1); /* McASP0 Control Registers */
    GEL_MapAdd(0x01b4c044,0,0x00000010,1,1);
    GEL_MapAdd(0x01b4c060,0,0x00000030,1,1);
    GEL_MapAdd(0x01b4c0a0,0,0x00000020,1,1);
    GEL_MapAdd(0x01b4c100,0,0x00000060,1,1);
    GEL_MapAdd(0x01b4c180,0,0x00000040,1,1);
    GEL_MapAdd(0x01b4c200,0,0x00000040,1,1);
    GEL_MapAdd(0x01b4c280,0,0x00000040,1,1);
    GEL_MapAdd(0x01b50000,0,0x00000020,1,1); /* McASP1 Control Registers */ 
    GEL_MapAdd(0x01b50044,0,0x00000010,1,1);
    GEL_MapAdd(0x01b50060,0,0x00000030,1,1);
    GEL_MapAdd(0x01b500a0,0,0x00000020,1,1);
    GEL_MapAdd(0x01b50100,0,0x00000060,1,1);
    GEL_MapAdd(0x01b50180,0,0x00000040,1,1);
    GEL_MapAdd(0x01b50200,0,0x00000040,1,1);
    GEL_MapAdd(0x01b50280,0,0x00000040,1,1);
    GEL_MapAdd(0x02000000,0,0x00000014,0,1); /* QDMA Registers */
    GEL_MapAdd(0x02000020,0,0x00000014,0,1);
    GEL_MapAdd(0x03000000,0,0x00800000,1,0); /* ROM */
    GEL_MapAdd(0x30000000,0,0x04000000,1,1); /* McBSP0 Data */
    GEL_MapAdd(0x34000000,0,0x04000000,1,1); /* McBSP1 Data */
    GEL_MapAdd(0x80000000,0,0x10000000,1,1); /* External Memory Interface CE0 */
    GEL_MapAdd(0x90000000,0,0x10000000,1,1); /* External Memory Interface CE1 */
    GEL_MapAdd(0xa0000000,0,0x10000000,1,1); /* External Memory Interface CE2 */
    GEL_MapAdd(0xb0000000,0,0x10000000,1,1); /* External Memory Interface CE3 */

}

OnTargetConnect()
{
    /* initialize the EMIF registers on the C6x when Code Composer starts up */

	emif_init();  
}



/* OnReset callback function called after the target processor has been reset */
OnReset(int nErrorCode)
{
    if (nErrorCode)
    {
       GEL_TextOut("An error occured while resetting -%d-\n",nErrorCode);
    }
    else
    {
       emif_init();
    }
}


/*
 * Menuitem creates a selection available beneath the GEL
 * menu selection in Code Composer Studio.
 */
menuitem "Resets";

hotmenu ClearBreakPts_Reset_EMIFset()
{
  GEL_BreakPtReset();
  GEL_Reset();
  emif_init();
}


/*********************************************/


emif_init()
{
    #define EMIF_GCTL       0x01800000
    #define EMIF_CE1        0x01800004
    #define EMIF_CE0        0x01800008
    #define EMIF_CE2        0x01800010
    #define EMIF_CE3        0x01800014
    #define EMIF_SDRAMCTL   0x01800018
    #define EMIF_SDRAMTIM   0x0180001C
    #define EMIF_SDRAMEXT   0x01800020
    #define EMIF_CCFG       0x01840000;  /* Cache configuration register */
    
    /* EMIF setup */
	*(int *)EMIF_GCTL = EMIF_GCTL | 0x000000b8;//HOLD invalid,ECLKOUT enabled,Clkout1 & Clkout2 enabled
	*(int *)EMIF_CE0 = 0x00000090;//16 bits SDRAM
	*(int *)EMIF_CE1 = 0x00000010;//16 bits wideth asynchronous interface
	*(int *)EMIF_CE2 = 0x00000000;//8 bits width asynchronous interface
	*(int *)EMIF_CE3 = 0x00000000;//8 bits width asynchronous interface
	*(int *)EMIF_SDRAMCTL = 0x57113000;//SDRAM parameters config
	*(int *)EMIF_SDRAMTIM = 0x005dc5dc;//SDRAM parameters config(refresh)
	*(int *)EMIF_SDRAMEXT = 0x000544a3;//SDRAM parameters config
}