#define	CSR6_PB		    0x00000008	/* pass bad frames */#define	CSR6_HO		    0x00000004	/* hash only filter mode [RO] */#define	CSR6_SR		    0x00000002	/* start/stop receive command */#define	CSR6_HP		    0x00000001	/* hash/perfect filter mode [RO] *//* CSR7 Interrupt Mask register */#define CSR7_169_LCM	0x08000000  /* link changed mask - 169 */#define CSR7_169_GPM	0x04000000  /* general purpose port mask - 169 */#define	CSR7_NIM	    0x00010000	/* normal interrupt mask */#define	CSR7_AIM	    0x00008000	/* abnormal interrupt mask */#define CSR7_169_ERM    0x00004000  /* early receive mask - 169 */#define	CSR7_SEM	    0x00002000	/* system error mask */#define	CSR7_169_LFM    0x00001000	/* link fail mask */#define	CSR7_169_FDM	0x00000800	/* full duplex mask - 169 */#define	CSR7_169_TMR	0x00000800	/* gp timer mask */#define	CSR7_169_ATM	0x00000400	/* aui/tp switch mask - 169 */#define	CSR7_169_ETM	0x00000400	/* early trasmit mask */#define	CSR7_RWM	    0x00000200	/* rcv watchdog time-out mask */#define	CSR7_RSM	    0x00000100	/* rcv stopped mask */#define	CSR7_RUM	    0x00000080	/* rcv buff unavailable mask */#define	CSR7_RIM	    0x00000040	/* rcv  interrupt mask */#define	CSR7_UNM	    0x00000020	/* underflow interrupt mask */ #define CSR7_169_LPE	0x00000010  /* link pass - 169 */#define	CSR7_TJM	    0x00000008	/* xmit jabber timer out mask */ #define	CSR7_TUM	    0x00000004	/* xmit buff unavailable mask */#define	CSR7_TSM	    0x00000002	/* xmission stopped mask */#define	CSR7_TIM	    0x00000001	/* xmit interrupt mask *//* CSR8 Missing Frame Counter */#define	CSR8_169_OFO		0x10000000   /* overflow counter overflow */#define	CSR8_169_OFC_MSK	0x0FFE0000   /* overflow counter */#define	CSR8_MFO		    0x00010000   /* missed frame overflow */#define CSR8_MFC_MSK		0x0000FFFF   /* Missed frame counter mask *//* CSR9 Ethernet Address ROM Register */#define	CSR9_169_MDI	0x00080000	/* MII mgmt data in */#define	CSR9_169_MII	0x00040000	/* MII mgmt op mode */#define	CSR9_169_MDO	0x00020000	/* MII mgmt write data */#define	CSR9_169_MDC	0x00010000	/* MII mgmt clock */#define	CSR9_169_RD	0x00004000	/* Serial ROM Read */#define	CSR9_169_WR	0x00002000	/* Serial ROM Write */#define	CSR9_169_BR	0x00001000	/* boot rom select */#define	CSR9_169_SR	0x00000800	/* serial rom select */#define	CSR9_169_REG	0x00000400	/* external register select */#define	CSR9_169_DNV	0x80000000	/* Data not valid */#define CSR9_DAT_MSK	0x000000FF	/* data mask */#define ENET_ROM_SIZE	8		/* ethernet rom register size *//* CSR10 Reserved *//* CSR11 Full Duplex Register */#define	CSR11_FDACV_MSK	0x0000FFFF	/* full duplex auto config mask *//* CSR12 SIA status Register - 169 */#define	CSR12_169_DA0	 0x00000080	/* Diagnostic bit all One */#define	CSR12_169_DAZ	 0x00000040	/* Diagnostic bit all zero */#define	CSR12_169_DSP	 0x00000020	/* Diagnostic BIST status indicator */#define	CSR12_169_DSD	 0x00000010	/* Diagnostic Self test done */#define	CSR12_169_APS	 0x00000008	/* Auto polarity state */#define	CSR12_169_LKF	 0x00000004	/* link fail status */#define	CSR12_169_NCR	 0x00000002	/* network connection error */#define	CSR12_169_PAUI  0x00000001	/* pin AUI_TP indication *//* CSR12 General Purpose Register - 169 */#define CSR12_169_GPC	0x00000100  /* General purpose control */#define CSR12_169_MD	0x000000ff	/* General purpose mode/data *//* CSR12 SIA status Register  */ #define CSR12_169_LPN	0x00008000      /* link partern negotiable */#define CSR12_169_LCK	0x00006000      /* link check */#define CSR12_169_FLP	0x00005000      /* FLP link good */#define CSR12_169_CAK	0x00004000      /* complete acknowledge */#define CSR12_169_AKD	0x00003000      /* acknowledge detect */#define CSR12_169_ADT	0x00002000      /* ability detect */#define CSR12_169_TRD	0x00001000      /* Transmit disable */#define CSR12_169_DIS	0x00000000      /* autonegotiation disable */#define CSR12_169_TRF	0x00000800      /* transmit remote fault */#define CSR12_169_NSN	0x00000400      /* non stable NLPs detected */#define CSR12_169_TRA	0x00000200      /* 10Base-T receive port activity */#define CSR12_169_ARA	0x00000100      /* AUI receive port activity */#define CSR12_169_APS	0x00000008      /* Auto polarity state */#define CSR12_169_10	0x00000004      /* 10 Mb/s link status */#define CSR12_169_100	0x00000002      /* 100 Mb/s link status */#define CSR12_169_MRA  0x00000001      /* MII receive port activity *//* CSR13 SIA connectivity Register */#define CSR13_OE57	    0x00008000	/* Output enable 5 6 7 */#define CSR13_OE24	    0x00004000	/* output enable 2 4 */#define CSR13_OE13	    0x00002000	/* output enable 1 3 */#define CSR13_IE	    0x00001000	/* input enable */	#define CSR13_SEL_LED	0x00000f00	/* select LED and external driver */#define CSR13_ASE_APLL	0x00000080	/* ase apll start enable */#define CSR13_SIM	    0x00000040	/* serial iface input multiplexer */#define CSR13_ENI	    0x00000020	/* encoder Input multiplexer */#define CSR13_EDP_SIA	0x00000010	/* pll external input enable */#define CSR13_AUI_TP	0x00000008	/* AUI - 10BASE-T or AUI */#define CSR13_CAC_CSR	0x00000004	/* auto config register */#define	CSR13_PS	    0x00000002	/* pin AUI_TP select */	#define CSR13_SRL_SIA	0x00000001	/* srl sia Reset *//* CSR14 SIA xmit rcv Register */#define CSR14_169_T4	0x00040000  /* 1000Base-T4 -169 */#define CSR14_169_TXF	0x00020000  /* 100Base-TX full duplex - 169 */#define CSR14_169_TXH	0x00010000  /* 100Base-TX half duplex - 169 */#define CSR14_169_TAS	0x00008000  /* 10Base-T/AUI autosensing - 169 */#define CSR14_SPP	    0x00004000	/* set polarity plus */#define CSR14_APE	    0x00002000	/* auto polarity enable */#define CSR14_LTE	    0x00001000	/* link test enable */#define CSR14_SQE	    0x00000800	/* signal quality generate enable */#define CSR14_CLD	    0x00000400	/* collision detect enable */#define CSR14_CSQ	    0x00000200	/* collision squelch enable */#define CSR14_RSQ	    0x00000100	/* receive squelch enable */#define CSR14_169_ANE  0x00000080  /* autonegotiation enable */#define CSR14_169_TH   0x00000040  /* 10Base-T half duplex enable */#define CSR14_CPEN_NC	0x00000030	/* no compensation */#define CSR14_CPEN_HP	0x00000020	/* high power mode */#define CSR14_CPEN_DM	0x00000010	/* disable mode */#define CSR14_LSE	    0x00000008	/* link pulse send enable */#define CSR14_DREN	    0x00000004	/* driver enable */#define CSR14_LBK	    0x00000002	/* loopback enable */#define CSR14_ECEN	    0x00000001	/* encoder enable *//* CSR15 SIA general register */#define CSR15_169_RMI	0x40000000      /* receive match interrupt */#define CSR15_169_GI1	0x20000000      /* general port interrupt 1 */#define CSR15_169_GI0	0x10000000      /* general port interrupt 0 */#define CSR15_169_CWE	0x08000000      /* control write enable */#define CSR15_169_RME	0x04000000      /* receive match enable */#define CSR15_169_GE1	0x02000000      /* GEP interrupt enable on  port 1 */#define CSR15_169_GE0	0x01000000      /* GEP interrupt enable on  port 0 */#define CSR15_169_LG3	0x00800000      /* LED/GEP3 select */#define CSR15_169_LG2	0x00400000      /* LED/GEP2 select */#define CSR15_169_LG1	0x00200000      /* LED/GEP1 select */#define CSR15_169_LG0	0x00100000      /* LED/GEP0 select */#define CSR15_169_RWR	0x00000020      /* receive watchdog release */#define CSR15_169_RWD	0x00000010      /* receive watchdog disable */#define CSR15_169_ABM	0x00000008      /* AUI/BNC mode */#define CSR15_JCK	    0x00000004	    /* jabber clock */#define CSR15_HUJ	    0x00000002	    /* host unjab */#define CSR15_JBD	    0x00000001	    /* jabber disable */#define CSR15_MD_MSK    0x000F0000      /* general purpose mode mask */#define CSR15_MODE_10	0x00050000 #define CSR15_MD_VAL(x) (((x) << 16) & CSR15_MD_MSK) /* receive descriptor *//* receive descriptor 0 */#define RDESC0_OWN		0x80000000	/* Own */#define RDESC0_FF       0x40000000  /* filtering fail */#define RDESC0_ES		0x00008000	/* Error summary */#define RDESC0_LE		0x00004000#define RDESC0_DT_SRF	0x00000000	/* serial rcvd frame */#define RDESC0_DT_ILF	0x00001000	/* internal loop back frame */#define RDESC0_DT_ELF	0x00002000	/* external loop back frame */#define RDESC0_RF		0x00000800	/* runt frame */#define RDESC0_MF		0x00000400	/* multicast frame */#define RDESC0_FD		0x00000200	/* first descriptor */#define RDESC0_LS		0x00000100	/* last descriptor */#define RDESC0_TL		0x00000080	/* frame too long */#define RDESC0_CS		0x00000040	/* collision seen */#define RDESC0_FT		0x00000020	/* frame type */#define RDESC0_RJ		0x00000010	/* receive watch dog */#define RDESC0_RE       0x00000008  /* report on MII error */#define RDESC0_DB		0x00000004	/* dribbling bit */#define RDESC0_CE		0x00000002	/* crc error */#define RDESC0_OF		0x00000001	/* Over flow */#define PNIC_FRAME_LEN_MSK	0x7FFF0000	/* Frame length mask */#define PNIC_FRAME_LEN_GET(x)	(((x) & PNIC_FRAME_LEN_MSK) >> 16)#define PNIC_FRAME_LEN_SET(x)	(((x) << 16) & PNIC_FRAME_LEN_MSK)/* receive descriptor 1 */#define RDESC1_RER		0x02000000	/* recv end of ring */#define RDESC1_RCH		0x01000000	/* second address chained */#define RDESC1_RBS2_MSK		0x003FF800	/* RBS2 buffer 2 size */#define RDESC1_RBS1_MSK		0x000007FF	/* RBS1 buffer 1 size */#define RDESC1_RBS1_VAL(x)	((x) & RDESC1_RBS1_MSK)	/* multiple of 4 */#define RDESC1_RBS2_VAL(x)	(((x) << 11) & RDESC1_RBS2_MSK)	/* transmit descriptor *//* xmit descriptor 0 */#define TDESC0_OWN		0x80000000	/* own */#define TDESC0_ES		0x00008000	/* error summary */#define TDESC0_TO		0x00004000	/* xmit jabber time out */#define TDESC0_LO		0x00000800	/* loss of carrier */#define TDESC0_NC		0x00000400	/* NC No carrier */#define TDESC0_LC		0x00000200	/* late collision */	#define TDESC0_EC		0x00000100	/* excessive collision */#define TDESC0_HF		0x00000080	/* heart beat fail */#define TDESC0_LF		0x00000004	/* link fail */#define TDESC0_UF		0x00000002	/* underflow error */#define TDESC0_DE	    0x00000001	/* deffered */#define TDESC0_CC_MSK		0x00000078#define	TDESC0_CC_VAL(X)	(((X) & TDESC0_CC_MSK) >> 3)    /* xmit descriptor 1 */#define TDESC1_IC		0x80000000	/* interrupt on completion */#define TDESC1_LS		0x40000000	/* last segment */#define TDESC1_FS		0x20000000	/* first segment */#define TDESC1_FT1		0x10000000	/* filtering type */#define TDESC1_SET		0x08000000	/* setup packet */#define TDESC1_AC		0x04000000	/* add crc disable */#define TDESC1_TER		0x02000000	/* xmit end of ring */#define TDESC1_TCH		0x01000000	/* second address chained */#define TDESC1_DPD		0x00800000	/* disabled padding */#define TDESC1_FT0		0x00400000	/* filtering type */#define TDESC1_TBS2_MSK		0x003FF800	/* TBS2 buffer 2 size */#define TDESC1_TBS1_MSK		0x000007FF	/* TBS2 buffer 1 size */#define TDESC1_TBS1_PUT(x)	((x) & TDESC1_TBS1_MSK)	/* multiple of 4 */#define TDESC1_TBS2_PUT(x)	(((x) << 11) & TDESC1_TBS2_MSK)#define FLTR_FRM_SIZE		0xC0		/* filter frm size 192 bytes */#define FLTR_FRM_SIZE_ULONGS	(FLTR_FRM_SIZE / sizeof (ULONG))#define FLTR_FRM_ADRS_NUM	0x10		/* filter frm holds 16 addrs */#define FLTR_FRM_ADRS_SIZE	0x06		/* size of each phys addrs */#define FLTR_FRM_DEF_ADRS	0xFFFFFFFF	/* enet broad cast address */#define FLTR_FRM_PHY_ADRS_OFF	156             /* word - 39 */#define PNIC_CRC_POLY		0x04c11db6   /* for CRC computation */#define PNIC_FLT_INDEX(I)	((((I) & ~0x1) * 2) + ((I) & 0x1))/* MII Defines */#define	MII_MGMT_WR_OFF		 17#define	MII_MGMT_WR		     ((ULONG) 0x00020000)#define	MII_WRITE		     ((ULONG) 0x00002000)#define	MII_READ		     ((ULONG) 0x00044000)#define	MII_MGMT_CLOCK		 ((ULONG) 0x00010000)#define	MII_READ_FRM		 ((ULONG) 0x60000000)#define	MII_PHY_CTRL_RES	 ((USHORT) 0x007F)#define	MII_PHY_STAT_RES	 ((USHORT) 0x07C0)#define	MII_PHY_NWAY_RES	 ((USHORT) 0x1C00)#define	MII_PHY_NWAY_EXP_RES ((USHORT) 0xFFE0)#define	MII_MGMT_DATA_IN	 ((ULONG) 0x00080000)#define	MII_READ_DATA_MSK	 MII_MGMT_DATA_IN