?? class.ptf.bak
字號:
}
FILE
{
filepath = "hdl/can_register_syn.v";
use_in_simulation = "1";
use_in_synthesis = "1";
}
FILE
{
filepath = "hdl/can_registers.v";
use_in_simulation = "1";
use_in_synthesis = "1";
}
FILE
{
filepath = "hdl/can_top.v";
use_in_simulation = "1";
use_in_synthesis = "1";
}
}
}
COMPONENT_BUILDER
{
CACHED_HDL_INFO
{
# cached hdl info, emitted by cbGuinevereApp.CBFrameRealtime.getDocumentCachedHDLInfoSection:130
# used only by Component Builder
FILE can_acf.v
{
file_mod = "Mon May 31 07:46:12 PDT 2004";
quartus_map_start = "Tue Feb 22 12:02:10 PST 2005";
quartus_map_finished = "Tue Feb 22 12:02:11 PST 2005";
#found 1 valid modules
WRAPPER can_acf
{
CLASS can_acf
{
MODULE_DEFAULTS
{
class = "can_acf";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Width = "0";
Address_Alignment = "dynamic";
Data_Width = "8";
Has_Base_Address = "0";
Has_IRQ = "0";
}
PORT_WIRING
{
PORT clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
}
PORT rst
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT id
{
width = "29";
width_expression = "";
direction = "input";
type = "export";
}
PORT reset_mode
{
width = "1";
width_expression = "";
direction = "input";
type = "reset";
}
PORT acceptance_filter_mode
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT extended_mode
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT acceptance_code_0
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT acceptance_code_1
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT acceptance_code_2
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT acceptance_code_3
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT acceptance_mask_0
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT acceptance_mask_1
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT acceptance_mask_2
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT acceptance_mask_3
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT go_rx_crc_lim
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT go_rx_inter
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT go_error_frame
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT data0
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT data1
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT rtr1
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT rtr2
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT ide
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT no_byte0
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT no_byte1
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT id_ok
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
}
}
}
PORT_WIRING
{
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "can_acf";
technology = "imported components";
}
}
CB_GENERATOR
{
top_module_name = "can_acf";
emit_system_h = "0";
HDL_FILES
{
FILE
{
filepath = "C:/altera/projects/CAN/can_acf.v";
use_in_simulation = "1";
use_in_synthesis = "1";
}
}
}
COMPONENT_BUILDER
{
HDL_PARAMETERS
{
# generated by cbDocument.CBDocument.getParameterContainer:348
# used only by Component Editor
HDL_PARAMETER tp
{
parameter_name = "Tp";
type = "integer";
default_value = "1";
editable = "1";
tooltip = "";
}
}
}
}
}
}
FILE can_bsp.v
{
file_mod = "Mon Nov 22 11:18:04 PST 2004";
quartus_map_start = "Tue Feb 22 12:02:12 PST 2005";
quartus_map_finished = "Tue Feb 22 12:02:14 PST 2005";
#found 1 valid modules
WRAPPER can_bsp
{
CLASS can_bsp
{
MODULE_DEFAULTS
{
class = "can_bsp";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Width = "0";
Address_Alignment = "dynamic";
Data_Width = "8";
Has_Base_Address = "0";
Has_IRQ = "1";
}
PORT_WIRING
{
PORT clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
}
PORT rst
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT sample_point
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT sampled_bit
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT sampled_bit_q
{
width = "1";
width_expression = "";
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