?? class.ptf.bak
字號:
}
PORT rx_inter
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT transmitting
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT transmitter
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT go_rx_inter
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT tx_next
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT go_overload_frame
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT go_error_frame
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT go_tx
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT send_ack
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT node_error_passive
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT sample_point
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
}
PORT sampled_bit
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
}
PORT sampled_bit_q
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
}
PORT tx_point
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
}
PORT hard_sync
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
}
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "can_btl";
technology = "imported components";
}
}
CB_GENERATOR
{
top_module_name = "can_btl";
emit_system_h = "0";
HDL_FILES
{
FILE
{
filepath = "C:/altera/projects/CAN/can_btl.v";
use_in_simulation = "1";
use_in_synthesis = "1";
}
}
}
COMPONENT_BUILDER
{
HDL_PARAMETERS
{
# generated by cbDocument.CBDocument.getParameterContainer:348
# used only by Component Editor
HDL_PARAMETER tp
{
parameter_name = "Tp";
type = "integer";
default_value = "1";
editable = "1";
tooltip = "";
}
}
}
}
}
}
FILE can_crc.v
{
file_mod = "Sun Feb 08 06:25:58 PST 2004";
quartus_map_start = "Tue Feb 22 12:02:15 PST 2005";
quartus_map_finished = "Tue Feb 22 12:02:16 PST 2005";
#found 1 valid modules
WRAPPER can_crc
{
CLASS can_crc
{
MODULE_DEFAULTS
{
class = "can_crc";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Width = "0";
Address_Alignment = "dynamic";
Data_Width = "8";
Has_Base_Address = "0";
Has_IRQ = "0";
}
PORT_WIRING
{
PORT clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
}
PORT data
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT enable
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT initialize
{
width = "1";
direction = "input";
type = "export";
}
PORT crc
{
width = "15";
width_expression = "";
direction = "output";
type = "export";
}
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "can_crc";
technology = "imported components";
}
}
CB_GENERATOR
{
top_module_name = "can_crc";
emit_system_h = "0";
HDL_FILES
{
FILE
{
filepath = "C:/altera/projects/CAN/can_crc.v";
use_in_simulation = "1";
use_in_synthesis = "1";
}
}
}
COMPONENT_BUILDER
{
HDL_PARAMETERS
{
# generated by cbDocument.CBDocument.getParameterContainer:348
# used only by Component Editor
HDL_PARAMETER tp
{
parameter_name = "Tp";
type = "integer";
default_value = "1";
editable = "1";
tooltip = "";
}
}
}
}
}
}
FILE can_defines.v
{
file_mod = "Tue Feb 22 11:39:19 PST 2005";
quartus_map_start = "Tue Feb 22 12:02:16 PST 2005";
quartus_map_finished = "Tue Feb 22 12:02:17 PST 2005";
#found 0 valid modules
}
FILE can_fifo.v
{
file_mod = "Thu Nov 18 04:39:34 PST 2004";
quartus_map_start = "Tue Feb 22 12:02:17 PST 2005";
quartus_map_finished = "Tue Feb 22 12:02:19 PST 2005";
#found 1 valid modules
WRAPPER can_fifo
{
CLASS can_fifo
{
MODULE_DEFAULTS
{
class = "can_fifo";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Width = "0";
Address_Alignment = "dynamic";
Data_Width = "8";
Has_Base_Address = "0";
Has_IRQ = "0";
}
PORT_WIRING
{
PORT clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
}
PORT rst
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT wr
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT data_in
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT addr
{
width = "6";
width_expression = "";
direction = "input";
type = "export";
}
PORT reset_mode
{
width = "1";
width_expression = "";
direction = "input";
type = "reset";
}
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