//////////////////////////////////////////////////////////////////////////                                                              ////////  can_top.v                                                   ////////                                                              ////////                                                              ////////  This file is part of the CAN Protocol Controller            ////////  http://www.opencores.org/projects/can/                      ////////                                                              ////////                                                              ////////  Author(s):                                                  ////////       Igor Mohor                                             ////////       igorm@opencores.org                                    ////////                                                              ////////                                                              ////////  All additional information is available in the README.txt   ////////  file.                                                       ////////                                                              //////////////////////////////////////////////////////////////////////////////                                                              //////// Copyright (C) 2002, 2003, 2004 Authors                       ////////                                                              //////// This source file may be used and distributed without         //////// restriction provided that this copyright statement is not    //////// removed from the file and that any derivative work contains  //////// the original copyright notice and the associated disclaimer. ////////                                                              //////// This source file is free software; you can redistribute it   //////// and/or modify it under the terms of the GNU Lesser General   //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any   //////// later version.                                               ////////                                                              //////// This source is distributed in the hope that it will be       //////// useful, but WITHOUT ANY WARRANTY; without even the implied   //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //////// PURPOSE.  See the GNU Lesser General Public License for more //////// details.                                                     ////////                                                              //////// You should have received a copy of the GNU Lesser General    //////// Public License along with this source; if not, download it   //////// from http://www.opencores.org/lgpl.shtml                     ////////                                                              //////// The CAN protocol is developed by Robert Bosch GmbH and       //////// protected by patents. Anybody who wants to implement this    //////// CAN IP core on silicon has to obtain a CAN protocol license  //////// from Bosch.                                                  ////////                                                              ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: can_top.v,v $// Revision 1.48  2004/10/25 11:44:47  igorm// Interrupt is always cleared for one clock after the irq register is read.// This fixes problems when CPU is using IRQs that are edge triggered.//// Revision 1.47  2004/02/08 14:53:54  mohor// Header changed. Address latched to posedge. bus_off_on signal added.//// Revision 1.46  2003/10/17 05:55:20  markom// mbist signals updated according to newest convention//// Revision 1.45  2003/09/30 00:55:13  mohor// Error counters fixed to be compatible with Bosch VHDL reference model.// Small synchronization changes.//// Revision 1.44  2003/09/25 18:55:49  mohor// Synchronization changed, error counters fixed.//// Revision 1.43  2003/08/20 09:57:39  mohor// Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need// to be joined together on higher level.//// Revision 1.42  2003/07/16 15:11:28  mohor// Fixed according to the linter.//// Revision 1.41  2003/07/10 15:32:27  mohor// Unused signal removed.//// Revision 1.40  2003/07/10 01:59:04  tadejm// Synchronization fixed. In some strange cases it didn't work according to// the VHDL reference model.//// Revision 1.39  2003/07/07 11:21:37  mohor// Little fixes (to fix warnings).//// Revision 1.38  2003/07/03 09:32:20  mohor// Synchronization changed.//// Revision 1.37  2003/06/27 20:56:15  simons// Virtual silicon ram instances added.//// Revision 1.36  2003/06/17 14:30:30  mohor// "chip select" signal cs_can_i is used only when not using WISHBONE// interface.//// Revision 1.35  2003/06/16 13:57:58  mohor// tx_point generated one clk earlier. rx_i registered. Data corrected when// using extended mode.//// Revision 1.34  2003/06/13 15:02:24  mohor// Synchronization is also needed when transmitting a message.//// Revision 1.33  2003/06/11 14:21:35  mohor// When switching to tx, sync stage is overjumped.//// Revision 1.32  2003/06/09 11:32:36  mohor// Ports added for the CAN_BIST.//// Revision 1.31  2003/03/26 11:19:46  mohor// CAN interrupt is active low.//// Revision 1.30  2003/03/20 17:01:17  mohor// unix.//// Revision 1.28  2003/03/14 19:36:48  mohor// can_cs signal used for generation of the cs.//// Revision 1.27  2003/03/12 05:56:33  mohor// Bidirectional port_0_i changed to port_0_io.// input cs_can changed to cs_can_i.//// Revision 1.26  2003/03/12 04:39:40  mohor// rd_i and wr_i are active high signals. If 8051 is connected, these two signals// need to be negated one level higher.//// Revision 1.25  2003/03/12 04:17:36  mohor// 8051 interface added (besides WISHBONE interface). Selection is made in// can_defines.v file.//// Revision 1.24  2003/03/10 17:24:40  mohor// wire declaration added.//// Revision 1.23  2003/03/05 15:33:13  mohor// tx_o is now tristated signal. tx_oen and tx_o combined together.//// Revision 1.22  2003/03/05 15:01:56  mohor// Top level signal names changed.//// Revision 1.21  2003/03/01 22:53:33  mohor// Actel APA ram supported.//// Revision 1.20  2003/02/19 15:09:02  mohor// Incomplete sensitivity list fixed.//// Revision 1.19  2003/02/19 15:04:14  mohor// Typo fixed.//// Revision 1.18  2003/02/19 14:44:03  mohor// CAN core finished. Host interface added. Registers finished.// Synchronization to the wishbone finished.//// Revision 1.17  2003/02/18 00:10:15  mohor// Most of the registers added. Registers "arbitration lost capture", "error code// capture" + few more still need to be added.//// Revision 1.16  2003/02/14 20:17:01  mohor// Several registers added. Not finished, yet.//// Revision 1.15  2003/02/12 14:25:30  mohor// abort_tx added.//// Revision 1.14  2003/02/11 00:56:06  mohor// Wishbone interface added.//// Revision 1.13  2003/02/09 18:40:29  mohor// Overload fixed. Hard synchronization also enabled at the last bit of// interframe.//// Revision 1.12  2003/02/09 02:24:33  mohor// Bosch license warning added. Error counters finished. Overload frames// still need to be fixed.//// Revision 1.11  2003/02/04 14:34:52  mohor// *** empty log message ***//// Revision 1.10  2003/01/31 01:13:38  mohor// backup.//// Revision 1.9  2003/01/15 13:16:48  mohor// When a frame with "remote request" is received, no data is stored to// fifo, just the frame information (identifier, ...). Data length that// is stored is the received data length and not the actual data length// that is stored to fifo.//// Revision 1.8  2003/01/14 17:25:09  mohor// Addresses corrected to decimal values (previously hex).//// Revision 1.7  2003/01/10 17:51:34  mohor// Temporary version (backup).//// Revision 1.6  2003/01/09 21:54:45  mohor// rx fifo added. Not 100 % verified, yet.//// Revision 1.5  2003/01/08 02:10:56  mohor// Acceptance filter added.//// Revision 1.4  2002/12/28 04:13:23  mohor// Backup version.//// Revision 1.3  2002/12/27 00:12:52  mohor// Header changed, testbench improved to send a frame (crc still missing).//// Revision 1.2  2002/12/26 16:00:34  mohor// Testbench define file added. Clock divider register added.//// Revision 1.1.1.1  2002/12/20 16:39:21  mohor// Initial//////// synopsys translate_off`include "timescale.v"// synopsys translate_on`include "can_defines.v"module can_top(   `ifdef CAN_WISHBONE_IF    wb_clk_i,    wb_rst_i,    wb_dat_i,    wb_dat_o,    wb_cyc_i,    wb_stb_i,    wb_we_i,    wb_adr_i,    wb_ack_o,  `else     `ifdef CAN_AVALON_IF     av_rst_i,     av_cs_i,     av_wr_i,     av_adr_i,     av_dat_i,     av_dat_o,   `else     rst_i,     ale_i,     rd_i,     wr_i,     port_0_io,     cs_can_i,   `endif  `endif  clk_i,  rx_i,  tx_o,  bus_off_on,  irq_on,  clkout_o  // Bist`ifdef CAN_BIST  ,  // debug chain signals  mbist_si_i,       // bist scan serial in  mbist_so_o,       // bist scan serial out  mbist_ctrl_i        // bist chain shift control`endif);parameter Tp = 1;`ifdef CAN_WISHBONE_IF  input        wb_clk_i;  input        wb_rst_i;  input  [7:0] wb_dat_i;  output [7:0] wb_dat_o;  input        wb_cyc_i;  input        wb_stb_i;  input        wb_we_i;  input  [7:0] wb_adr_i;  output       wb_ack_o;  reg          wb_ack_o;  reg          cs_sync1;  reg          cs_sync2;  reg          cs_sync3;    reg          cs_ack1;  reg          cs_ack2;  reg          cs_ack3;  reg          cs_sync_rst1;  reg          cs_sync_rst2;  wire         cs_can_i;`else `ifdef CAN_AVALON_IF   input        av_rst_i;   input        av_cs_i;     input        av_wr_i;   input  [7:0] av_dat_i;   output [7:0] av_dat_o;   input  [7:0] av_adr_i;     wire         av_cs_i; `else   input        rst_i;   input        ale_i;   input        rd_i;   input        wr_i;   inout  [7:0] port_0_io;   input        cs_can_i;     reg    [7:0] addr_latched;   reg          wr_i_q;   reg          rd_i_q; `endif`endifinput        clk_i;input        rx_i;output       tx_o;output       bus_off_on;output       irq_on;output       clkout_o;// Bist`ifdef CAN_BISTinput   mbist_si_i;       // bist scan serial inoutput  mbist_so_o;       // bist scan serial outinput [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control`endifreg          data_out_fifo_selected;wire   [7:0] data_out_fifo;wire   [7:0] data_out_regs;/* Mode register */wire         reset_mode;wire         listen_only_mode;wire         acceptance_filter_mode;wire         self_test_mode;/* Command register */wire         release_buffer;wire         tx_request;wire         abort_tx;wire         self_rx_request;wire         single_shot_transmission;wire         tx_state;wire         tx_state_q;wire         overload_request;wire         overload_frame;/* Arbitration Lost Capture Register */wire         read_arbitration_lost_capture_reg;/* Error Code Capture Register */wire         read_error_code_capture_reg;wire   [7:0] error_capture_code;/* Bus Timing 0 register */wire   [5:0] baud_r_presc;wire   [1:0] sync_jump_width;/* Bus Timing 1 register */wire   [3:0] time_segment1;wire   [2:0] time_segment2;wire         triple_sampling;/* Error Warning Limit register */wire   [7:0] error_warning_limit;/* Rx Error Counter register */wire         we_rx_err_cnt;/* Tx Error Counter register */wire         we_tx_err_cnt;/* Clock Divider register */wire         extended_mode;/* This section is for BASIC and EXTENDED mode *//* Acceptance code register */wire   [7:0] acceptance_code_0;/* Acceptance mask register */wire   [7:0] acceptance_mask_0;/* End: This section is for BASIC and EXTENDED mode *//* This section is for EXTENDED mode *//* Acceptance code register */wire   [7:0] acceptance_code_1;wire   [7:0] acceptance_code_2;wire   [7:0] acceptance_code_3;/* Acceptance mask register */wire   [7:0] acceptance_mask_1;wire   [7:0] acceptance_mask_2;wire   [7:0] acceptance_mask_3;/* End: This section is for EXTENDED mode *//* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */wire   [7:0] tx_data_0;wire   [7:0] tx_data_1;wire   [7:0] tx_data_2;wire   [7:0] tx_data_3;wire   [7:0] tx_data_4;wire   [7:0] tx_data_5;wire   [7:0] tx_data_6;wire   [7:0] tx_data_7;wire   [7:0] tx_data_8;wire   [7:0] tx_data_9;wire   [7:0] tx_data_10;wire   [7:0] tx_data_11;wire   [7:0] tx_data_12;/* End: Tx data registers */wire         cs;/* Output signals from can_btl module */wire         sample_point;wire         sampled_bit;wire         sampled_bit_q;wire         tx_point;wire         hard_sync;/* output from can_bsp module */wire         rx_idle;wire         transmitting;wire         transmitter;wire         go_rx_inter;wire         not_first_bit_of_inter;wire         set_reset_mode;wire         node_bus_off;wire         error_status;wire   [7:0] rx_err_cnt;wire   [7:0] tx_err_cnt;wire         rx_err_cnt_dummy;  // The MSB is not displayed. It is just used for easier calculation (no counter overflow).wire         tx_err_cnt_dummy;  // The MSB is not displayed. It is just used for easier calculation (no counter overflow).wire         transmit_status;wire         receive_status;wire         tx_successful;wire         need_to_tx;wire         overrun;wire         info_empty;wire         set_bus_error_irq;wire         set_arbitration_lost_irq;wire   [4:0] arbitration_lost_capture;wire         node_error_passive;wire         node_error_active;wire   [6:0] rx_message_counter;wire         tx_next;wire         go_overload_frame;wire         go_error_frame;wire         go_tx;