output        transmit_status;output        receive_status;output        tx_successful;output        need_to_tx;output        overrun;output        info_empty;output        set_bus_error_irq;output        set_arbitration_lost_irq;output  [4:0] arbitration_lost_capture;output        node_error_passive;output        node_error_active;output  [6:0] rx_message_counter;/* This section is for BASIC and EXTENDED mode *//* Acceptance code register */input   [7:0] acceptance_code_0;/* Acceptance mask register */input   [7:0] acceptance_mask_0;/* End: This section is for BASIC and EXTENDED mode *//* This section is for EXTENDED mode *//* Acceptance code register */input   [7:0] acceptance_code_1;input   [7:0] acceptance_code_2;input   [7:0] acceptance_code_3;/* Acceptance mask register */input   [7:0] acceptance_mask_1;input   [7:0] acceptance_mask_2;input   [7:0] acceptance_mask_3;/* End: This section is for EXTENDED mode *//* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */input   [7:0] tx_data_0;input   [7:0] tx_data_1;input   [7:0] tx_data_2;input   [7:0] tx_data_3;input   [7:0] tx_data_4;input   [7:0] tx_data_5;input   [7:0] tx_data_6;input   [7:0] tx_data_7;input   [7:0] tx_data_8;input   [7:0] tx_data_9;input   [7:0] tx_data_10;input   [7:0] tx_data_11;input   [7:0] tx_data_12;/* End: Tx data registers *//* Tx signal */output        tx;output        tx_next;output        bus_off_on;output        go_overload_frame;output        go_error_frame;output        go_tx;output        send_ack;/* Bist */`ifdef CAN_BISTinput         mbist_si_i;output        mbist_so_o;input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control`endifreg           reset_mode_q;reg     [5:0] bit_cnt;reg     [3:0] data_len;reg    [28:0] id;reg     [2:0] bit_stuff_cnt;reg     [2:0] bit_stuff_cnt_tx;reg           tx_point_q;reg           rx_idle;reg           rx_id1;reg           rx_rtr1;reg           rx_ide;reg           rx_id2;reg           rx_rtr2;reg           rx_r1;reg           rx_r0;reg           rx_dlc;reg           rx_data;reg           rx_crc;reg           rx_crc_lim;reg           rx_ack;reg           rx_ack_lim;reg           rx_eof;reg           rx_inter;reg           go_early_tx_latched;reg           rtr1;reg           ide;reg           rtr2;reg    [14:0] crc_in;reg     [7:0] tmp_data;reg     [7:0] tmp_fifo [0:7];reg           write_data_to_tmp_fifo;reg     [2:0] byte_cnt;reg           bit_stuff_cnt_en;reg           crc_enable;reg     [2:0] eof_cnt;reg     [2:0] passive_cnt;reg           transmitting;reg           error_frame;reg           enable_error_cnt2;reg     [2:0] error_cnt1;reg     [2:0] error_cnt2;reg     [2:0] delayed_dominant_cnt;reg           enable_overload_cnt2;reg           overload_frame;reg           overload_frame_blocked;reg     [1:0] overload_request_cnt;reg     [2:0] overload_cnt1;reg     [2:0] overload_cnt2;reg           tx;reg           crc_err;reg           arbitration_lost;reg           arbitration_lost_q;reg           arbitration_field_d;reg     [4:0] arbitration_lost_capture;reg     [4:0] arbitration_cnt;reg           arbitration_blocked;reg           tx_q;reg           need_to_tx;   // When the CAN core has something to transmit and a dominant bit is sampled at the third bitreg     [3:0] data_cnt;     // Counting the data bytes that are written to FIFOreg     [2:0] header_cnt;   // Counting header lengthreg           wr_fifo;      // Write data and header to 64-byte fiforeg     [7:0] data_for_fifo;// Multiplexed data that is stored to 64-byte fiforeg     [5:0] tx_pointer;reg           tx_bit;reg           tx_state;reg           tx_state_q;reg           transmitter;reg           finish_msg;reg     [8:0] rx_err_cnt;reg     [8:0] tx_err_cnt;reg     [3:0] bus_free_cnt;reg           bus_free_cnt_en;reg           bus_free;reg           waiting_for_bus_free;reg           node_error_passive;reg           node_bus_off;reg           node_bus_off_q;reg           ack_err_latched;reg           bit_err_latched;reg           stuff_err_latched;reg           form_err_latched;reg           rule3_exc1_1;reg           rule3_exc1_2;reg           suspend;reg           susp_cnt_en;reg     [2:0] susp_cnt;reg           error_flag_over_latched;reg     [7:0] error_capture_code;reg     [7:6] error_capture_code_type;reg           error_capture_code_blocked;reg           tx_next;reg           first_compare_bit;wire    [4:0] error_capture_code_segment;wire          error_capture_code_direction;wire          bit_de_stuff;wire          bit_de_stuff_tx;wire          rule5;/* Rx state machine */wire          go_rx_idle;wire          go_rx_id1;wire          go_rx_rtr1;wire          go_rx_ide;wire          go_rx_id2;wire          go_rx_rtr2;wire          go_rx_r1;wire          go_rx_r0;wire          go_rx_dlc;wire          go_rx_data;wire          go_rx_crc;wire          go_rx_crc_lim;wire          go_rx_ack;wire          go_rx_ack_lim;wire          go_rx_eof;wire          go_rx_inter;wire          last_bit_of_inter;wire          go_crc_enable;wire          rst_crc_enable;wire          bit_de_stuff_set;wire          bit_de_stuff_reset;wire          go_early_tx;wire   [14:0] calculated_crc;wire   [15:0] r_calculated_crc;wire          remote_rq;wire    [3:0] limited_data_len;wire          form_err;wire          error_frame_ended;wire          overload_frame_ended;wire          bit_err;wire          ack_err;wire          stuff_err;wire          id_ok;                // If received ID matches ID set in registerswire          no_byte0;             // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.wire          no_byte1;             // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.wire    [2:0] header_len;wire          storing_header;wire    [3:0] limited_data_len_minus1;wire          reset_wr_fifo;wire          err;wire          arbitration_field;wire   [18:0] basic_chain;wire   [63:0] basic_chain_data;wire   [18:0] extended_chain_std;wire   [38:0] extended_chain_ext;wire   [63:0] extended_chain_data_std;wire   [63:0] extended_chain_data_ext;wire          rst_tx_pointer;wire    [7:0] r_tx_data_0;wire    [7:0] r_tx_data_1;wire    [7:0] r_tx_data_2;wire    [7:0] r_tx_data_3;wire    [7:0] r_tx_data_4;wire    [7:0] r_tx_data_5;wire    [7:0] r_tx_data_6;wire    [7:0] r_tx_data_7;wire    [7:0] r_tx_data_8;wire    [7:0] r_tx_data_9;wire    [7:0] r_tx_data_10;wire    [7:0] r_tx_data_11;wire    [7:0] r_tx_data_12;wire          send_ack;wire          bit_err_exc1;wire          bit_err_exc2;wire          bit_err_exc3;wire          bit_err_exc4;wire          bit_err_exc5;wire          bit_err_exc6;wire          error_flag_over;wire          overload_flag_over;wire    [5:0] limited_tx_cnt_ext;wire    [5:0] limited_tx_cnt_std;assign go_rx_idle     =                   sample_point &  sampled_bit & last_bit_of_inter | bus_free & (~node_bus_off);assign go_rx_id1      =                   sample_point &  (~sampled_bit) & (rx_idle | last_bit_of_inter);assign go_rx_rtr1     = (~bit_de_stuff) & sample_point &  rx_id1  & (bit_cnt[3:0] == 4'd10);assign go_rx_ide      = (~bit_de_stuff) & sample_point &  rx_rtr1;assign go_rx_id2      = (~bit_de_stuff) & sample_point &  rx_ide  &   sampled_bit;assign go_rx_rtr2     = (~bit_de_stuff) & sample_point &  rx_id2  & (bit_cnt[4:0] == 5'd17);assign go_rx_r1       = (~bit_de_stuff) & sample_point &  rx_rtr2;assign go_rx_r0       = (~bit_de_stuff) & sample_point & (rx_ide  & (~sampled_bit) | rx_r1);assign go_rx_dlc      = (~bit_de_stuff) & sample_point &  rx_r0;assign go_rx_data     = (~bit_de_stuff) & sample_point &  rx_dlc  & (bit_cnt[1:0] == 2'd3) &  (sampled_bit   |   (|data_len[2:0])) & (~remote_rq);assign go_rx_crc      = (~bit_de_stuff) & sample_point & (rx_dlc  & (bit_cnt[1:0] == 2'd3) & ((~sampled_bit) & (~(|data_len[2:0])) | remote_rq) |                                                          rx_data & (bit_cnt[5:0] == ((limited_data_len<<3) - 1'b1)));  // overflow works ok at max value (8<<3 = 64 = 0). 0-1 = 6'h3fassign go_rx_crc_lim  = (~bit_de_stuff) & sample_point &  rx_crc  & (bit_cnt[3:0] == 4'd14);assign go_rx_ack      = (~bit_de_stuff) & sample_point &  rx_crc_lim;assign go_rx_ack_lim  =                   sample_point &  rx_ack;assign go_rx_eof      =                   sample_point &  rx_ack_lim;assign go_rx_inter    =                 ((sample_point &  rx_eof  & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & (~overload_request);assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;assign go_overload_frame = (     sample_point & ((~sampled_bit) | overload_request) & (rx_eof & (~transmitter) & (eof_cnt == 3'd6) | error_frame_ended | overload_frame_ended) |                                  sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2)                                                            |                                 sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))                           )                           & (~overload_frame_blocked)                           ;assign go_crc_enable  = hard_sync | go_tx;assign rst_crc_enable = go_rx_crc;assign bit_de_stuff_set   = go_rx_id1 & (~go_error_frame);assign bit_de_stuff_reset = go_rx_ack | go_error_frame | go_overload_frame;assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);assign limited_data_len = (data_len < 4'h8)? data_len : 4'h8;assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx != sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5) & (~bit_err_exc6) & (~reset_mode);assign bit_err_exc1 = tx_state & arbitration_field & tx;assign bit_err_exc2 = rx_ack & tx;assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 3'd7);assign bit_err_exc4 = (error_frame & (error_cnt1 == 3'd7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2));assign bit_err_exc5 = (error_frame & (error_cnt2 == 3'd7)) | (overload_frame & (overload_cnt2 == 3'd7));assign bit_err_exc6 = (eof_cnt == 3'd6) & rx_eof & (~transmitter); assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;assign last_bit_of_inter = rx_inter & (bit_cnt[1:0] == 2'd2);assign not_first_bit_of_inter = rx_inter & (bit_cnt[1:0] != 2'd0);// Rx idle statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_idle <= 1'b0;  else if (go_rx_id1 | go_error_frame)    rx_idle <=#Tp 1'b0;  else if (go_rx_idle)    rx_idle <=#Tp 1'b1;end// Rx id1 statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_id1 <= 1'b0;  else if (go_rx_rtr1 | go_error_frame)    rx_id1 <=#Tp 1'b0;  else if (go_rx_id1)    rx_id1 <=#Tp 1'b1;end// Rx rtr1 statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_rtr1 <= 1'b0;  else if (go_rx_ide | go_error_frame)    rx_rtr1 <=#Tp 1'b0;  else if (go_rx_rtr1)    rx_rtr1 <=#Tp 1'b1;end// Rx ide statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_ide <= 1'b0;  else if (go_rx_r0 | go_rx_id2 | go_error_frame)    rx_ide <=#Tp 1'b0;  else if (go_rx_ide)    rx_ide <=#Tp 1'b1;end// Rx id2 statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_id2 <= 1'b0;  else if (go_rx_rtr2 | go_error_frame)    rx_id2 <=#Tp 1'b0;  else if (go_rx_id2)    rx_id2 <=#Tp 1'b1;end// Rx rtr2 statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_rtr2 <= 1'b0;  else if (go_rx_r1 | go_error_frame)    rx_rtr2 <=#Tp 1'b0;  else if (go_rx_rtr2)    rx_rtr2 <=#Tp 1'b1;end// Rx r0 statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_r1 <= 1'b0;  else if (go_rx_r0 | go_error_frame)    rx_r1 <=#Tp 1'b0;  else if (go_rx_r1)    rx_r1 <=#Tp 1'b1;end// Rx r0 statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_r0 <= 1'b0;  else if (go_rx_dlc | go_error_frame)    rx_r0 <=#Tp 1'b0;  else if (go_rx_r0)    rx_r0 <=#Tp 1'b1;end// Rx dlc statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_dlc <= 1'b0;  else if (go_rx_data | go_rx_crc | go_error_frame)    rx_dlc <=#Tp 1'b0;  else if (go_rx_dlc)