rx_dlc <=#Tp 1'b1;end// Rx data statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_data <= 1'b0;  else if (go_rx_crc | go_error_frame)    rx_data <=#Tp 1'b0;  else if (go_rx_data)    rx_data <=#Tp 1'b1;end// Rx crc statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_crc <= 1'b0;  else if (go_rx_crc_lim | go_error_frame)    rx_crc <=#Tp 1'b0;  else if (go_rx_crc)    rx_crc <=#Tp 1'b1;end// Rx crc delimiter statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_crc_lim <= 1'b0;  else if (go_rx_ack | go_error_frame)    rx_crc_lim <=#Tp 1'b0;  else if (go_rx_crc_lim)    rx_crc_lim <=#Tp 1'b1;end// Rx ack statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_ack <= 1'b0;  else if (go_rx_ack_lim | go_error_frame)    rx_ack <=#Tp 1'b0;  else if (go_rx_ack)    rx_ack <=#Tp 1'b1;end// Rx ack delimiter statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_ack_lim <= 1'b0;  else if (go_rx_eof | go_error_frame)    rx_ack_lim <=#Tp 1'b0;  else if (go_rx_ack_lim)    rx_ack_lim <=#Tp 1'b1;end// Rx eof statealways @ (posedge clk or posedge rst)begin  if (rst)    rx_eof <= 1'b0;  else if (go_rx_inter | go_error_frame | go_overload_frame)    rx_eof <=#Tp 1'b0;  else if (go_rx_eof)    rx_eof <=#Tp 1'b1;end// Interframe spacealways @ (posedge clk or posedge rst)begin  if (rst)    rx_inter <= 1'b0;  else if (go_rx_idle | go_rx_id1 | go_overload_frame | go_error_frame)    rx_inter <=#Tp 1'b0;  else if (go_rx_inter)    rx_inter <=#Tp 1'b1;end// ID registeralways @ (posedge clk or posedge rst)begin  if (rst)    id <= 29'h0;  else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))    id <=#Tp {id[27:0], sampled_bit};end// rtr1 bitalways @ (posedge clk or posedge rst)begin  if (rst)    rtr1 <= 1'b0;  else if (sample_point & rx_rtr1 & (~bit_de_stuff))    rtr1 <=#Tp sampled_bit;end// rtr2 bitalways @ (posedge clk or posedge rst)begin  if (rst)    rtr2 <= 1'b0;  else if (sample_point & rx_rtr2 & (~bit_de_stuff))    rtr2 <=#Tp sampled_bit;end// ide bitalways @ (posedge clk or posedge rst)begin  if (rst)    ide <= 1'b0;  else if (sample_point & rx_ide & (~bit_de_stuff))    ide <=#Tp sampled_bit;end// Data lengthalways @ (posedge clk or posedge rst)begin  if (rst)    data_len <= 4'b0;  else if (sample_point & rx_dlc & (~bit_de_stuff))    data_len <=#Tp {data_len[2:0], sampled_bit};end// Dataalways @ (posedge clk or posedge rst)begin  if (rst)    tmp_data <= 8'h0;  else if (sample_point & rx_data & (~bit_de_stuff))    tmp_data <=#Tp {tmp_data[6:0], sampled_bit};endalways @ (posedge clk or posedge rst)begin  if (rst)    write_data_to_tmp_fifo <= 1'b0;  else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))    write_data_to_tmp_fifo <=#Tp 1'b1;  else    write_data_to_tmp_fifo <=#Tp 1'b0;endalways @ (posedge clk or posedge rst)begin  if (rst)    byte_cnt <= 3'h0;  else if (write_data_to_tmp_fifo)    byte_cnt <=#Tp byte_cnt + 1'b1;  else if (sample_point & go_rx_crc_lim)    byte_cnt <=#Tp 3'h0;endalways @ (posedge clk)begin  if (write_data_to_tmp_fifo)    tmp_fifo[byte_cnt] <=#Tp tmp_data;end// CRCalways @ (posedge clk or posedge rst)begin  if (rst)    crc_in <= 15'h0;  else if (sample_point & rx_crc & (~bit_de_stuff))    crc_in <=#Tp {crc_in[13:0], sampled_bit};end// bit_cntalways @ (posedge clk or posedge rst)begin  if (rst)    bit_cnt <= 6'd0;  else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |            go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)    bit_cnt <=#Tp 6'd0;  else if (sample_point & (~bit_de_stuff))    bit_cnt <=#Tp bit_cnt + 1'b1;end// eof_cntalways @ (posedge clk or posedge rst)begin  if (rst)    eof_cnt <= 3'd0;  else if (sample_point)    begin      if (go_rx_inter | go_error_frame | go_overload_frame)        eof_cnt <=#Tp 3'd0;      else if (rx_eof)        eof_cnt <=#Tp eof_cnt + 1'b1;    endend// Enabling bit de-stuffingalways @ (posedge clk or posedge rst)begin  if (rst)    bit_stuff_cnt_en <= 1'b0;  else if (bit_de_stuff_set)    bit_stuff_cnt_en <=#Tp 1'b1;  else if (bit_de_stuff_reset)    bit_stuff_cnt_en <=#Tp 1'b0;end// bit_stuff_cntalways @ (posedge clk or posedge rst)begin  if (rst)    bit_stuff_cnt <= 3'h1;  else if (bit_de_stuff_reset)    bit_stuff_cnt <=#Tp 3'h1;  else if (sample_point & bit_stuff_cnt_en)    begin      if (bit_stuff_cnt == 3'h5)        bit_stuff_cnt <=#Tp 3'h1;      else if (sampled_bit == sampled_bit_q)        bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;      else        bit_stuff_cnt <=#Tp 3'h1;    endend// bit_stuff_cnt_txalways @ (posedge clk or posedge rst)begin  if (rst)    bit_stuff_cnt_tx <= 3'h1;  else if (reset_mode || bit_de_stuff_reset)    bit_stuff_cnt_tx <=#Tp 3'h1;  else if (tx_point_q & bit_stuff_cnt_en)    begin      if (bit_stuff_cnt_tx == 3'h5)        bit_stuff_cnt_tx <=#Tp 3'h1;      else if (tx == tx_q)        bit_stuff_cnt_tx <=#Tp bit_stuff_cnt_tx + 1'b1;      else        bit_stuff_cnt_tx <=#Tp 3'h1;    endendassign bit_de_stuff = bit_stuff_cnt == 3'h5;assign bit_de_stuff_tx = bit_stuff_cnt_tx == 3'h5;// stuff_errassign stuff_err = sample_point & bit_stuff_cnt_en & bit_de_stuff & (sampled_bit == sampled_bit_q);// Generating delayed signalsalways @ (posedge clk or posedge rst)begin  if (rst)    begin      reset_mode_q <=#Tp 1'b0;      node_bus_off_q <=#Tp 1'b0;    end  else    begin      reset_mode_q <=#Tp reset_mode;      node_bus_off_q <=#Tp node_bus_off;    endendalways @ (posedge clk or posedge rst)begin  if (rst)    crc_enable <= 1'b0;  else if (rst_crc_enable)    crc_enable <=#Tp 1'b0;  else if (go_crc_enable)    crc_enable <=#Tp 1'b1;end// CRC error generationalways @ (posedge clk or posedge rst)begin  if (rst)    crc_err <= 1'b0;  else if (reset_mode | error_frame_ended)    crc_err <=#Tp 1'b0;  else if (go_rx_ack)    crc_err <=#Tp crc_in != calculated_crc;end// Conditions for form errorassign form_err = sample_point & ( ((~bit_de_stuff) & rx_crc_lim & (~sampled_bit)                  ) |                                   (                  rx_ack_lim & (~sampled_bit)                  ) |                                   ((eof_cnt < 3'd6)& rx_eof     & (~sampled_bit) & (~transmitter) ) |                                   (                & rx_eof     & (~sampled_bit) &   transmitter  )                                 );always @ (posedge clk or posedge rst)begin  if (rst)    ack_err_latched <= 1'b0;  else if (reset_mode | error_frame_ended | go_overload_frame)    ack_err_latched <=#Tp 1'b0;  else if (ack_err)    ack_err_latched <=#Tp 1'b1;endalways @ (posedge clk or posedge rst)begin  if (rst)    bit_err_latched <= 1'b0;  else if (reset_mode | error_frame_ended | go_overload_frame)    bit_err_latched <=#Tp 1'b0;  else if (bit_err)    bit_err_latched <=#Tp 1'b1;end// Rule 5 (Fault confinement).assign rule5 = bit_err &  ( (~node_error_passive) & error_frame    & (error_cnt1    < 3'd7)                            |                                                     overload_frame & (overload_cnt1 < 3'd7)                          );// Rule 3 exception 1 - first part (Fault confinement).always @ (posedge clk or posedge rst)begin  if (rst)    rule3_exc1_1 <= 1'b0;  else if (error_flag_over | rule3_exc1_2)    rule3_exc1_1 <=#Tp 1'b0;  else if (transmitter & node_error_passive & ack_err)    rule3_exc1_1 <=#Tp 1'b1;end// Rule 3 exception 1 - second part (Fault confinement).always @ (posedge clk or posedge rst)begin  if (rst)    rule3_exc1_2 <= 1'b0;  else if (go_error_frame | rule3_exc1_2)    rule3_exc1_2 <=#Tp 1'b0;  else if (rule3_exc1_1 & (error_cnt1 < 3'd7) & sample_point & (~sampled_bit))    rule3_exc1_2 <=#Tp 1'b1;endalways @ (posedge clk or posedge rst)begin  if (rst)    stuff_err_latched <= 1'b0;  else if (reset_mode | error_frame_ended | go_overload_frame)    stuff_err_latched <=#Tp 1'b0;  else if (stuff_err)    stuff_err_latched <=#Tp 1'b1;endalways @ (posedge clk or posedge rst)begin  if (rst)    form_err_latched <= 1'b0;  else if (reset_mode | error_frame_ended | go_overload_frame)    form_err_latched <=#Tp 1'b0;  else if (form_err)    form_err_latched <=#Tp 1'b1;end// Instantiation of the RX CRC modulecan_crc i_can_crc_rx (  .clk(clk),  .data(sampled_bit),  .enable(crc_enable & sample_point & (~bit_de_stuff)),  .initialize(go_crc_enable),  .crc(calculated_crc));assign no_byte0 = rtr1 | (data_len<4'h1);assign no_byte1 = rtr1 | (data_len<4'h2);can_acf i_can_acf(  .clk(clk),  .rst(rst),    .id(id),  /* Mode register */  .reset_mode(reset_mode),  .acceptance_filter_mode(acceptance_filter_mode),  // Clock Divider register