if (r_tx_data_0[0])    // Extended frame            tx_bit = extended_chain_ext[tx_pointer];          else            tx_bit = extended_chain_std[tx_pointer];        end    end  else  // Basic mode    begin      if (rx_data)  // data stage        tx_bit = basic_chain_data[tx_pointer];      else if (rx_crc)        tx_bit = r_calculated_crc[tx_pointer];      else if (finish_msg)        tx_bit = 1'b1;      else        tx_bit = basic_chain[tx_pointer];    endendassign limited_tx_cnt_ext = tx_data_0[3] ? 6'h3f : ((tx_data_0[2:0] <<3) - 1'b1);assign limited_tx_cnt_std = tx_data_1[3] ? 6'h3f : ((tx_data_1[2:0] <<3) - 1'b1);assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) &   extended_mode  &   r_tx_data_0[0]   & tx_pointer == 6'd38             ) |   // arbitration + control for extended format                        ((~bit_de_stuff_tx) & tx_point & (~rx_data) &   extended_mode  & (~r_tx_data_0[0])  & tx_pointer == 6'd18             ) |   // arbitration + control for extended format                        ((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode)                      & tx_pointer == 6'd18             ) |   // arbitration + control for standard format                        ((~bit_de_stuff_tx) & tx_point &   rx_data  &   extended_mode                       & tx_pointer == limited_tx_cnt_ext) |   // data       (overflow is OK here)                        ((~bit_de_stuff_tx) & tx_point &   rx_data  & (~extended_mode)                      & tx_pointer == limited_tx_cnt_std) |   // data       (overflow is OK here)                        (                     tx_point &   rx_crc_lim                                                                         ) |   // crc                        (go_rx_idle                                                                                                           ) |   // at the end                        (reset_mode                                                                                                           ) |                        (overload_frame                                                                                                       ) |                        (error_frame                                                                                                          ) ;always @ (posedge clk or posedge rst)begin  if (rst)    tx_pointer <= 6'h0;  else if (rst_tx_pointer)    tx_pointer <=#Tp 6'h0;  else if (go_early_tx | (tx_point & (tx_state | go_tx) & (~bit_de_stuff_tx)))    tx_pointer <=#Tp tx_pointer + 1'b1;endassign tx_successful = transmitter & go_rx_inter & (~go_error_frame) & (~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost);always @ (posedge clk or posedge rst)begin  if (rst)    need_to_tx <= 1'b0;  else if (tx_successful | reset_mode | (abort_tx & (~transmitting)) | ((~tx_state) & tx_state_q & single_shot_transmission))    need_to_tx <=#Tp 1'h0;  else if (tx_request & sample_point)    need_to_tx <=#Tp 1'b1;endassign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend | (susp_cnt == 3'h7)) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);assign go_tx       = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend | (sample_point & (susp_cnt == 3'h7))) & (go_early_tx | rx_idle);// go_early_tx latched (for proper bit_de_stuff generation)always @ (posedge clk or posedge rst)begin  if (rst)    go_early_tx_latched <= 1'b0;  else if (reset_mode || tx_point)    go_early_tx_latched <=#Tp 1'b0;  else if (go_early_tx)    go_early_tx_latched <=#Tp 1'b1;end// Tx statealways @ (posedge clk or posedge rst)begin  if (rst)    tx_state <= 1'b0;  else if (reset_mode | go_rx_inter | error_frame | arbitration_lost)    tx_state <=#Tp 1'b0;  else if (go_tx)    tx_state <=#Tp 1'b1;endalways @ (posedge clk or posedge rst)begin  if (rst)    tx_state_q <=#Tp 1'b0;  else if (reset_mode)    tx_state_q <=#Tp 1'b0;  else    tx_state_q <=#Tp tx_state;end// Node is a transmitteralways @ (posedge clk or posedge rst)begin  if (rst)    transmitter <= 1'b0;  else if (go_tx)    transmitter <=#Tp 1'b1;  else if (reset_mode | go_rx_idle | suspend & go_rx_id1)    transmitter <=#Tp 1'b0;end // Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.// Node might be both transmitter or receiver (sending error or overload frame)always @ (posedge clk or posedge rst)begin  if (rst)    transmitting <= 1'b0;  else if (go_error_frame | go_overload_frame | go_tx | send_ack)    transmitting <=#Tp 1'b1;  else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state))    transmitting <=#Tp 1'b0;endalways @ (posedge clk or posedge rst)begin  if (rst)    suspend <= 1'b0;  else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))    suspend <=#Tp 1'b0;  else if (not_first_bit_of_inter & transmitter & node_error_passive)    suspend <=#Tp 1'b1;endalways @ (posedge clk or posedge rst)begin  if (rst)    susp_cnt_en <= 1'b0;  else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))    susp_cnt_en <=#Tp 1'b0;  else if (suspend & sample_point & last_bit_of_inter)    susp_cnt_en <=#Tp 1'b1;endalways @ (posedge clk or posedge rst)begin  if (rst)    susp_cnt <= 3'h0;  else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))    susp_cnt <=#Tp 3'h0;  else if (susp_cnt_en & sample_point)    susp_cnt <=#Tp susp_cnt + 1'b1;endalways @ (posedge clk or posedge rst)begin  if (rst)    finish_msg <= 1'b0;  else if (go_rx_idle | go_rx_id1 | error_frame | reset_mode)    finish_msg <=#Tp 1'b0;  else if (go_rx_crc_lim)    finish_msg <=#Tp 1'b1;endalways @ (posedge clk or posedge rst)begin  if (rst)    arbitration_lost <= 1'b0;  else if (go_rx_idle | error_frame_ended)    arbitration_lost <=#Tp 1'b0;  else if (transmitter & sample_point & tx & arbitration_field & ~sampled_bit)    arbitration_lost <=#Tp 1'b1;endalways @ (posedge clk or posedge rst)begin  if (rst)    arbitration_lost_q <=#Tp 1'b0;  else    arbitration_lost_q <=#Tp arbitration_lost;endalways @ (posedge clk or posedge rst)begin  if (rst)    arbitration_field_d <=#Tp 1'b0;  else if (sample_point)    arbitration_field_d <=#Tp arbitration_field;endassign set_arbitration_lost_irq = arbitration_lost & (~arbitration_lost_q) & (~arbitration_blocked);always @ (posedge clk or posedge rst)begin  if (rst)    arbitration_cnt <= 5'h0;  else if (sample_point && !bit_de_stuff)    if (arbitration_field_d)      arbitration_cnt <=#Tp arbitration_cnt + 1'b1;    else      arbitration_cnt <=#Tp 5'h0;endalways @ (posedge clk or posedge rst)begin  if (rst)    arbitration_lost_capture <= 5'h0;  else if (set_arbitration_lost_irq)    arbitration_lost_capture <=#Tp arbitration_cnt;endalways @ (posedge clk or posedge rst)begin  if (rst)    arbitration_blocked <= 1'b0;  else if (read_arbitration_lost_capture_reg)    arbitration_blocked <=#Tp 1'b0;  else if (set_arbitration_lost_irq)    arbitration_blocked <=#Tp 1'b1;endalways @ (posedge clk or posedge rst)begin  if (rst)    rx_err_cnt <= 9'h0;  else if (we_rx_err_cnt & (~node_bus_off))    rx_err_cnt <=#Tp {1'b0, data_in};  else if (set_reset_mode)    rx_err_cnt <=#Tp 9'h0;  else    begin      if ((~listen_only_mode) & (~transmitter | arbitration_lost))        begin          if (go_rx_ack_lim & (~go_error_frame) & (~crc_err) & (rx_err_cnt > 9'h0))            begin              if (rx_err_cnt > 9'd127)                rx_err_cnt <=#Tp 9'd127;              else                rx_err_cnt <=#Tp rx_err_cnt - 1'b1;            end          else if (rx_err_cnt < 9'd128)            begin              if (go_error_frame & (~rule5))                                                                                          // 1  (rule 5 is just the opposite then rule 1 exception                rx_err_cnt <=#Tp rx_err_cnt + 1'b1;              else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7)     ) |  // 2                        (go_error_frame & rule5                                                                                  ) |  // 5                        (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7)                            )                  // 6                      )                rx_err_cnt <=#Tp rx_err_cnt + 4'h8;            end        end    endendalways @ (posedge clk or posedge rst)begin  if (rst)    tx_err_cnt <= 9'h0;  else if (we_tx_err_cnt)    tx_err_cnt <=#Tp {1'b0, data_in};  else    begin      if (set_reset_mode)        tx_err_cnt <=#Tp 9'd128;      else if ((tx_err_cnt > 9'd0) & (tx_successful | bus_free))        tx_err_cnt <=#Tp tx_err_cnt - 1'h1;      else if (transmitter & (~arbitration_lost))        begin          if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7)                                          ) |       // 6               (go_error_frame & rule5                                                                                  ) |       // 4  (rule 5 is the same as rule 4)               (go_error_frame & (~(transmitter & node_error_passive & ack_err)) & (~(transmitter & stuff_err &                 arbitration_field & sample_point & tx & (~sampled_bit)))                                                ) |       // 3                (error_frame & rule3_exc1_2                                                                              )         // 3             )            tx_err_cnt <=#Tp tx_err_cnt + 4'h8;        end    endendalways @ (posedge clk or posedge rst)begin  if (rst)    node_error_passive <= 1'b0;  else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128))    node_error_passive <=#Tp 1'b0;  else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 9'd128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))    node_error_passive <=#Tp 1'b1;endassign node_error_active = ~(node_error_passive | node_bus_off);always @ (posedge clk or posedge rst)begin  if (rst)    node_bus_off <= 1'b0;  else if ((rx_err_cnt == 9'h0) & (tx_err_cnt == 9'd0) & (~reset_mode) | (we_tx_err_cnt & (data_in < 8'd255)))    node_bus_off <=#Tp 1'b0;  else if ((tx_err_cnt >= 9'd256) | (we_tx_err_cnt & (data_in == 8'd255)))    node_bus_off <=#Tp 1'b1;endalways @ (posedge clk or posedge rst)begin  if (rst)    bus_free_cnt <= 4'h0;  else if (sample_point)    begin      if (sampled_bit & bus_free_cnt_en & (bus_free_cnt < 4'd10))        bus_free_cnt <=#Tp bus_free_cnt + 1'b1;      else        bus_free_cnt <=#Tp 4'h0;    endendalways @ (posedge clk or posedge rst)begin  if (rst)    bus_free_cnt_en <= 1'b0;  else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))    bus_free_cnt_en <=#Tp 1'b1;  else if (sample_point & sampled_bit & (bus_free_cnt==4'd10) & (~node_bus_off))    bus_free_cnt_en <=#Tp 1'b0;endalways @ (posedge clk or posedge rst)begin  if (rst)    bus_free <= 1'b0;  else if (sample_point & sampled_bit & (bus_free_cnt==4'd10) && waiting_for_bus_free)    bus_free <=#Tp 1'b1;  else    bus_free <=#Tp 1'b0;endalways @ (posedge clk or posedge rst)begin  if (rst)    waiting_for_bus_free <= 1'b1;  else if (bus_free & (~node_bus_off))    waiting_for_bus_free <=#Tp 1'b0;  else if (node_bus_off_q & (~reset_mode))    waiting_for_bus_free <=#Tp 1'b1;endassign bus_off_on = ~node_bus_off;assign set_reset_mode = node_bus_off & (~node_bus_off_q);assign error_status = extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit))    :                                     ((rx_err_cnt >= 9'd96) | (tx_err_cnt >= 9'd96))                                ;assign transmit_status = transmitting  || (extended_mode && waiting_for_bus_free);assign receive_status  = extended_mode ? (waiting_for_bus_free || (!rx_idle) && (!transmitting)) :                                          ((!waiting_for_bus_free) && (!rx_idle) && (!transmitting));/* Error code capture register */always @ (posedge clk or posedge rst)begin  if (rst)    error_capture_code <= 8'h0;  else if (read_error_code_capture_reg)    error_capture_code <=#Tp 8'h0;  else if (set_bus_error_irq)    error_capture_code <=#Tp {error_capture_code_type[7:6], error_capture_code_direction, error_capture_code_segment[4:0]};endassign error_capture_code_segment[0] = rx_idle | rx_ide | (rx_id2 & (bit_cnt<6'd13)) | rx_r1 | rx_r0 | rx_dlc | rx_ack | rx_ack_lim | error_frame & node_error_active;assign error_capture_code_segment[1] = rx_idle | rx_id1 | rx_id2 | rx_dlc | rx_data | rx_ack_lim | rx_eof | rx_inter | error_frame & node_error_passive;assign error_capture_code_segment[2] = (rx_id1 & (bit_cnt>6'd7)) | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2 | rx_r1 | error_frame & node_error_passive | overload_frame;assign error_capture_code_segment[3] = (rx_id2 & (bit_cnt>6'd4)) | rx_rtr2 | rx_r1 | rx_r0 | rx_dlc | rx_data | rx_crc | rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | overload_frame;assign error_capture_code_segment[4] = rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | rx_inter | error_frame | overload_frame;assign error_capture_code_direction  = ~transmitting;always @ (bit_err or form_err or stuff_err)begin  if (bit_err)    error_capture_code_type[7:6] = 2'b00;  else if (form_err)    error_capture_code_type[7:6] = 2'b01;  else if (stuff_err)    error_capture_code_type[7:6] = 2'b10;  else    error_capture_code_type[7:6] = 2'b11;endassign set_bus_error_irq = go_error_frame & (~error_capture_code_blocked);always @ (posedge clk or posedge rst)begin  if (rst)    error_capture_code_blocked <= 1'b0;  else if (read_error_code_capture_reg)    error_capture_code_blocked <=#Tp 1'b0;  else if (set_bus_error_irq)    error_capture_code_blocked <=#Tp 1'b1;endendmodule