library verilog;use verilog.vl_types.all;entity Stack_AM is    generic(        HOLD            : integer := 0;        CLEAR           : integer := 1;        POP             : integer := 3;        PUSH            : integer := 2    );    port(        clk_i           : in     vl_logic;        ops_i           : in     vl_logic_vector(1 downto 0);        d_i             : in     vl_logic_vector(11 downto 0);        full_o          : out    vl_logic;        stk_data_o      : out    vl_logic_vector(11 downto 0)    );end Stack_AM;