library verilog;use verilog.vl_types.all;entity Regcnt_AM is    generic(        HOLD            : integer := 0;        LOAD            : integer := 1;        DEC             : integer := 3    );    port(        load_i          : in     vl_logic;        d_i             : in     vl_logic_vector(11 downto 0);        clk_i           : in     vl_logic;        ops_i           : in     vl_logic_vector(1 downto 0);        zero_o          : out    vl_logic;        reg_data_o      : out    vl_logic_vector(11 downto 0)    );end Regcnt_AM;