?? vhdl.vhd
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-- generated by newgenasym Tue Dec 23 13:29:09 2008library ieee;use ieee.std_logic_1164.all;use work.all;entity dsub25gnd is port ( MT1: INOUT STD_LOGIC; MT2: INOUT STD_LOGIC; P1: INOUT STD_LOGIC; P10: INOUT STD_LOGIC; P11: INOUT STD_LOGIC; P12: INOUT STD_LOGIC; P13: INOUT STD_LOGIC; P14: INOUT STD_LOGIC; P15: INOUT STD_LOGIC; P16: INOUT STD_LOGIC; P17: INOUT STD_LOGIC; P18: INOUT STD_LOGIC; P19: INOUT STD_LOGIC; P2: INOUT STD_LOGIC; P20: INOUT STD_LOGIC; P21: INOUT STD_LOGIC; P22: INOUT STD_LOGIC; P23: INOUT STD_LOGIC; P24: INOUT STD_LOGIC; P25: INOUT STD_LOGIC; P3: INOUT STD_LOGIC; P4: INOUT STD_LOGIC; P5: INOUT STD_LOGIC; P6: INOUT STD_LOGIC; P7: INOUT STD_LOGIC; P8: INOUT STD_LOGIC; P9: INOUT STD_LOGIC);end dsub25gnd;?? 快捷鍵說明
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