?? c8051f040.h
字號(hào):
/*---------------------------------------------------------------------------
; Copyright (C) 2002 CYGNAL INTEGRATED PRODUCTS, INC.
; All rights reserved.
;
;
; FILE NAME : C8051F040.H
; TARGET MCUs : C8051F040, 'F041, 'F042, 'F043
; DESCRIPTION : Register/bit definitions for the C8051F04x product family.
;
; REVISION 1.2
; CHANGES from Rev. 1.1: Properly labled sbit def's for CAN0STA
;
;---------------------------------------------------------------------------*/
#define SFR_PAGE_0 0
#define SFR_PAGE_1 1
#define SFR_PAGE_2 2
#define SFR_PAGE_3 3
#define SFR_PAGE_F 15
/* BYTE Registers */
sfr P0 = 0x80; /* PORT 0 */
sfr SP = 0x81; /* STACK POINTER */
sfr DPL = 0x82; /* DATA POINTER - LOW BYTE */
sfr DPH = 0x83; /* DATA POINTER - HIGH BYTE */
sfr SFRPAGE = 0x84; /* SFR PAGE SELECT */
sfr SFRNEXT = 0x85; /* SFR STACK NEXT PAGE */
sfr SFRLAST = 0x86; /* SFR STACK LAST PAGE */
sfr PCON = 0x87; /* POWER CONTROL */
sfr TCON = 0x88; /* TIMER CONTROL */
sfr CPT0CN = 0x88; /* COMPARATOR 0 CONTROL */
sfr CPT1CN = 0x88; /* COMPARATOR 1 CONTROL */
sfr CPT2CN = 0x88; /* COMPARATOR 2 CONTROL */
sfr TMOD = 0x89; /* TIMER MODE */
sfr CPT0MD = 0x89; /* COMPARATOR 0 MODE */
sfr CPT1MD = 0x89; /* COMPARATOR 1 MODE */
sfr CPT2MD = 0x89; /* COMPARATOR 2 MODE */
sfr TL0 = 0x8A; /* TIMER 0 - LOW BYTE */
sfr OSCICN = 0x8A; /* INTERNAL OSCILLATOR CONTROL */
sfr TL1 = 0x8B; /* TIMER 1 - LOW BYTE */
sfr OSCICL = 0x8B; /* INTERNAL OSCILLATOR CALIBRATION */
sfr TH0 = 0x8C; /* TIMER 0 - HIGH BYTE */
sfr OSCXCN = 0x8C; /* EXTERNAL OSCILLATOR CONTROL */
sfr TH1 = 0x8D; /* TIMER 1 - HIGH BYTE */
sfr CKCON = 0x8E; /* TIMER 0/1 CLOCK CONTROL */
sfr PSCTL = 0x8F; /* FLASH WRITE/ERASE CONTROL */
sfr P1 = 0x90; /* PORT 1 */
sfr SSTA0 = 0x91; /* UART 0 STATUS */
sfr SFRPGCN = 0x96; /* SFR PAGE CONTROL */
sfr CLKSEL = 0x97; /* SYSTEM CLOCK SELECT */
sfr SCON0 = 0x98; /* UART 0 CONTROL */
sfr SCON1 = 0x98; /* UART 1 CONTROL */
sfr SBUF0 = 0x99; /* UART 0 BUFFER */
sfr SBUF1 = 0x99; /* UART 1 BUFFER */
sfr SPI0CFG = 0x9A; /* SPI 0 CONFIGURATION */
sfr SPI0DAT = 0x9B; /* SPI 0 DATA */
sfr P4MDOUT = 0x9C; /* PORT 4 OUTPUT MODE */
sfr SPI0CKR = 0x9D; /* SPI 0 CLOCK RATE CONTROL */
sfr P5MDOUT = 0x9D; /* PORT 5 OUTPUT MODE */
sfr P6MDOUT = 0x9E; /* PORT 6 OUTPUT MODE */
sfr P7MDOUT = 0x9F; /* PORT 7 OUTPUT MODE */
sfr P2 = 0xA0; /* PORT 2 */
sfr EMI0TC = 0xA1; /* EMIF TIMING CONTROL */
sfr EMI0CN = 0xA2; /* EMIF CONTROL */
sfr EMI0CF = 0xA3; /* EMIF CONFIGURATION */
sfr P0MDOUT = 0xA4; /* PORT 0 OUTPUT MODE */
sfr P1MDOUT = 0xA5; /* PORT 1 OUTPUT MODE */
sfr P2MDOUT = 0xA6; /* PORT 2 OUTPUT MODE CONFIGURATION */
sfr P3MDOUT = 0xA7; /* PORT 3 OUTPUT MODE CONFIGURATION */
sfr IE = 0xA8; /* INTERRUPT ENABLE */
sfr SADDR0 = 0xA9; /* UART 0 SLAVE ADDRESS */
sfr SADDR1 = 0xA9; /* UART 1 SLAVE ADDRESS */
sfr P1MDIN = 0xAD; /* PORT 1 INPUT MODE */
sfr P2MDIN = 0xAE; /* PORT 2 INPUT MODE */
sfr P3MDIN = 0xAF; /* PORT 3 INPUT MODE */
sfr P3 = 0xB0; /* PORT 3 */
sfr FLSCL = 0xB7; /* FLASH TIMING PRESCALAR */
sfr FLACL = 0xB7; /* FLASH ACCESS LIMIT */
sfr IP = 0xB8; /* INTERRUPT PRIORITY */
sfr SADEN0 = 0xB9; /* UART 0 SLAVE ADDRESS MASK */
sfr AMX2CF = 0xBA; /* ADC 2 MUX CONFIGURATION */
sfr AMX0PRT = 0xBD; /* ADC 0 MUX PORT PIN SELECT REGISTER */
sfr AMX0CF = 0xBA; /* ADC 0 CONFIGURATION REGISTER */
sfr AMX0SL = 0xBB; /* ADC 0 AND ADC 1 MODE SELECTION */
sfr AMX2SL = 0xBB; /* ADC 2 MUX CHANNEL SELECTION */
sfr ADC0CF = 0xBC; /* ADC 0 CONFIGURATION */
sfr ADC2CF = 0xBC; /* ADC 2 CONFIGURATION */
sfr ADC0L = 0xBE; /* ADC 0 DATA - LOW BYTE */
sfr ADC2 = 0xBE; /* ADC 2 DATA - LOW BYTE */
sfr ADC0H = 0xBF; /* ADC 0 DATA - HIGH BYTE */
sfr SMB0CN = 0xC0; /* SMBUS 0 CONTROL */
sfr CAN0STA = 0xC0; /* CAN 0 STATUS */
sfr SMB0STA = 0xC1; /* SMBUS 0 STATUS */
sfr SMB0DAT = 0xC2; /* SMBUS 0 DATA */
sfr SMB0ADR = 0xC3; /* SMBUS 0 SLAVE ADDRESS */
sfr ADC0GTL = 0xC4; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
sfr ADC2GT = 0xC4; /* ADC 2 GREATER-THAN REGISTER - LOW BYTE */
sfr ADC0GTH = 0xC5; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
sfr ADC0LTL = 0xC6; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
sfr ADC2LT = 0xC6; /* ADC 2 LESS-THAN REGISTER - LOW BYTE */
sfr ADC0LTH = 0xC7; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
sfr TMR2CN = 0xC8; /* TIMER 2 CONTROL */
sfr TMR3CN = 0xC8; /* TIMER 3 CONTROL */
sfr TMR4CN = 0xC8; /* TIMER 4 CONTROL */
sfr P4 = 0xC8; /* PORT 4 */
sfr TMR2CF = 0xC9; /* TIMER 2 CONFIGURATION */
sfr TMR3CF = 0xC9; /* TIMER 3 CONFIGURATION */
sfr TMR4CF = 0xC9; /* TIMER 4 CONFIGURATION */
sfr RCAP2L = 0xCA; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
sfr RCAP3L = 0xCA; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
sfr RCAP4L = 0xCA; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
sfr RCAP2H = 0xCB; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
sfr RCAP3H = 0xCB; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
sfr RCAP4H = 0xCB; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
sfr TMR2L = 0xCC; /* TIMER 2 - LOW BYTE */
sfr TMR3L = 0xCC; /* TIMER 3 - LOW BYTE */
sfr TMR4L = 0xCC; /* TIMER 4 - LOW BYTE */
sfr TMR2H = 0xCD; /* TIMER 2 - HIGH BYTE */
sfr TMR3H = 0xCD; /* TIMER 3 - HIGH BYTE */
sfr TMR4H = 0xCD; /* TIMER 4 - HIGH BYTE */
sfr SMB0CR = 0xCF; /* SMBUS 0 CLOCK RATE */
sfr PSW = 0xD0; /* PROGRAM STATUS WORD */
sfr REF0CN = 0xD1; /* VOLTAGE REFERENCE 0 CONTROL */
sfr DAC0L = 0xD2; /* DAC 0 REGISTER - LOW BYTE */
sfr DAC1L = 0xD2; /* DAC 1 REGISTER - LOW BYTE */
sfr DAC0H = 0xD3; /* DAC 0 REGISTER - HIGH BYTE */
sfr DAC1H = 0xD3; /* DAC 1 REGISTER - HIGH BYTE */
sfr DAC0CN = 0xD4; /* DAC 0 CONTROL */
sfr DAC1CN = 0xD4; /* DAC 1 CONTROL */
sfr HVA0CN = 0xD6; /* HVDA CONTROL REGISTER */
sfr PCA0CN = 0xD8; /* PCA 0 COUNTER CONTROL */
sfr CAN0DATL = 0xD8; /* CAN 0 DATA - LOW BYTE */
sfr P5 = 0xD8; /* PORT 5 */
sfr PCA0MD = 0xD9; /* PCA 0 COUNTER MODE */
sfr CAN0DATH = 0xD9; /* CAN 0 DATA - HIGH BYTE */
sfr PCA0CPM0 = 0xDA; /* PCA 0 MODULE 0 CONTROL */
sfr CAN0ADR = 0xDA; /* CAN 0 ADDRESS */
sfr PCA0CPM1 = 0xDB; /* PCA 0 MODULE 1 CONTROL */
sfr CAN0TST = 0xDB; /* CAN 0 TEST */
sfr PCA0CPM2 = 0xDC; /* PCA 0 MODULE 2 CONTROL */
sfr PCA0CPM3 = 0xDD; /* PCA 0 MODULE 3 CONTROL */
sfr PCA0CPM4 = 0xDE; /* PCA 0 MODULE 4 CONTROL */
sfr PCA0CPM5 = 0xDF; /* PCA 0 MODULE 5 CONTROL */
sfr ACC = 0xE0; /* ACCUMULATOR */
sfr PCA0CPL5 = 0xE1; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
sfr XBR0 = 0xE1; /* CROSSBAR CONFIGURATION REGISTER 0 */
sfr PCA0CPH5 = 0xE2; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
sfr XBR1 = 0xE2; /* CROSSBAR CONFIGURATION REGISTER 1 */
sfr XBR2 = 0xE3; /* CROSSBAR CONFIGURATION REGISTER 2 */
sfr XBR3 = 0xE4; /* CROSSBAR CONFIGURATION REGISTER 3 */
sfr EIE1 = 0xE6; /* EXTERNAL INTERRUPT ENABLE 1 */
sfr EIE2 = 0xE7; /* EXTERNAL INTERRUPT ENABLE 2 */
sfr ADC0CN = 0xE8; /* ADC 0 CONTROL */
sfr ADC2CN = 0xE8; /* ADC 2 CONTROL */
sfr P6 = 0xE8; /* PORT 6 */
sfr PCA0CPL2 = 0xE9; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
sfr PCA0CPH2 = 0xEA; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
sfr PCA0CPL3 = 0xEB; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
sfr PCA0CPH3 = 0xEC; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
sfr PCA0CPL4 = 0xED; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
sfr PCA0CPH4 = 0xEE; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
sfr RSTSRC = 0xEF; /* RESET SOURCE */
sfr B = 0xF0; /* B REGISTER */
sfr EIP1 = 0xF6; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
sfr EIP2 = 0xF7; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
sfr SPI0CN = 0xF8; /* SPI 0 CONTROL */
sfr CAN0CN = 0xF8; /* CAN 0 CONTROL */
sfr P7 = 0xF8; /* PORT 7 */
sfr PCA0L = 0xF9; /* PCA 0 TIMER - LOW BYTE */
sfr PCA0H = 0xFA; /* PCA 0 TIMER - HIGH BYTE */
sfr PCA0CPL0 = 0xFB; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
sfr PCA0CPH0 = 0xFC; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
sfr PCA0CPL1 = 0xFD; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
sfr PCA0CPH1 = 0xFE; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
sfr WDTCN = 0xFF; /* WATCHDOG TIMER CONTROL */
/* BIT Registers */
/* TCON 0x88 */
sbit TF1 = TCON ^ 7; /* TIMER 1 OVERFLOW FLAG */
sbit TR1 = TCON ^ 6; /* TIMER 1 ON/OFF CONTROL */
sbit TF0 = TCON ^ 5; /* TIMER 0 OVERFLOW FLAG */
sbit TR0 = TCON ^ 4; /* TIMER 0 ON/OFF CONTROL */
sbit IE1 = TCON ^ 3; /* EXT. INTERRUPT 1 EDGE FLAG */
sbit IT1 = TCON ^ 2; /* EXT. INTERRUPT 1 TYPE */
sbit IE0 = TCON ^ 1; /* EXT. INTERRUPT 0 EDGE FLAG */
sbit IT0 = TCON ^ 0; /* EXT. INTERRUPT 0 TYPE */
/* CPT0CN 0x88 */
sbit CP0EN = CPT0CN ^ 7; /* COMPARATOR 0 ENABLE */
sbit CP0OUT = CPT0CN ^ 6; /* COMPARATOR 0 OUTPUT */
sbit CP0RIF = CPT0CN ^ 5; /* COMPARATOR 0 RISING EDGE INTERRUPT */
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