?? drcparams_dv34.c
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/*------------- Automatically generated parameters file ----------------/
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/----------------------------- Do not edit -----------------------------*/
#include "drive_setting\DV34\DrcParams_DV34.h"
#include "Drive\Zfe\Shared\Dsp\DrcParams\DrcParams.h"
CONST DrcParam DrcInitParams[] = {
// Defines
{DRC_Global_Programming, 0x0001}, // DSP (0x0001): Initialize Loop and Freq. Detector
{DRC_Init, 0x2003}, // DSP (0x2003): Init Spindle clock out, AGC and Jiter Meter
{DRC_Global_Programming, 0x0000}, // DSP (0x0000): Remove init signals
{DRC_Init, 0x0000}, // DSP (0x0000): Remove init signals
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDGParams[] = {
// Drc generel parameters for all kinds of DVDs
{ADC_Dig_Offset_RF, 0x0000}, // DSP (0): DRC Offset 0 is added
{ADC_Dig_Offset_RF_Shadow, 0x0000}, // DSP (0): DRC Offset shadow
{DRC_Clock_Enable, 0x0388}, // DSP (0x0388): Enable colcks for: Channel, Jiter Meter & Debug DAC
{DRC_DPLL_Freq_Ratio_Initial_Value_MSB, 0x001C}, // DSP (0x001c): DPLL Freq Ratio Init MS
{DRC_DPLL_Freq_Ratio_Initial_Value_LSB, 0x00A4}, // DSP (0x00a4): DPLL Freq Ratio Init LS
{DRC_Viterbi_Peak_Limiter_And_Memory_Depth, 0x021F}, // DSP (0x021f): Viterbi Peak Limiter Memory depth=31, Peak Lim = 0.5
{DRC_Viterbi_Const___01_16__2_5__10_07, 0x7DAD}, // DSP (0x7dad): Viterbi const0116 = 13; const0205 = 13; const1007 = 31
{DRC_Viterbi_Const_11_06__3_4, 0x03ED}, // DSP (0x03ed): Viterbi const1106 = 13; const0304 = 31
{DRC_Viterbi_Const16_5_7, 0x7DAD}, // DSP (0x7dad): Viterbi Land const16 = 13; const5 = 13; const7 = 31
{DRC_Viterbi_Const6_4_Pit, 0x03ED}, // DSP (0x03ed): Viterbi Land const6 = 13; const4 = 31 ; Equal Pit Land coefficients
{DRC_Global_Programming, 0x0001}, // DSP (0x0001): Initialize Loop and Freq. Detector
{DRC_DPLL_Global_Programming, 0xF029}, // DSP (0xf029): DPLL: 'DVD'; Enable DPLL NB; Init DPLL; Round width to nearest; Time Out Counter = 3; Enable Timeout
{DRC_Equalizer_Programming, 0x1800}, // DSP (0x1800): Enable Equalizer LPF ; Eq. Pos. Gain = 32; Eq. Neg. Gain = 0;
{DRC_Coef0817_Programming, 0x0000}, // DSP (0x0000): 9 tap Equalizer: Coeff0_8 = 0 ; Coeff1_7 = 0
{DRC_Coef2635_Programming, 0x0088}, // DSP (0x0088): 9 tap Equalizer: Coeff2_6 = -8 ; coeff3_5 = 0
{DRC_Coef4_Programming, 0x8030}, // DSP (0x8030): 9 tap Equalizer: Coeff4 = 48 ; Mode = Interp. output ; Use 9 tap equalizer
{DRC_Infilter, 0x0001}, // DSP (0x0001): In Filter enabled with coefficient set 1
{DRC_Equalizer_HPF, 0x8A80}, // DSP (0x8a80): Eq. HPF - DC = 128; Notch BW = 10; Enable HPF ::Changed to meet the new capacitors::
{DRC_Threshold_Programming, 0x00D4}, // DSP (0x00d4): Use the fix for I96B;Threshold: ThBW = 8 ??; Int Gain = 13; ??? = 2
{DRC_DPLL_Filter_Wide_Band, 0x8840}, // DSP (0x8840): DPLL_WB KintegralNW = 1; ProGain = 1; IntGain = 5; Kv = 7
{DRC_DPLL_Filter_Narrow_Band, 0x8840}, // DSP (0x8840): DPLL_NB KvN-Kv = 1; ProGainN = 4; IntGainN = 5; KvN = 8
{DRC_DPLL_Filter_Minimum_Width, 0x0303}, // DSP (0x0303): DPLL Filt. Min Width: min len phase update WB = 3; min len phase update NB = 3;
{DRC_DPLL_Invalid_Sync, 0x03FF}, // DSP (0x03ff): DPLL Invalid Sync: Invalid Sync1 = 31; Invalid Sync3 = 31;
{DRC_DPLL_Number_Of_Good_Frame_For_NB, 0x0041}, // DSP (0x0041): DPLL Num Good 4 NB: Good Frames = 1; Num Good = 4
{DRC_DPLL_Frame_Window, 0x045C}, // DSP (0x045c): DPLL Frame Sync Window: Frame Sync Window = 1116
{DRC_Phase_Lock_Error_Init, 0x1964}, // DSP (0x1964): Phase Lock Err Init = 6500
{DRC_Phase_Unlock_Error_Max, 0x1900}, // DSP (0x1900): Phase Unlock Err Max = 6400
{DRC_Phase_Lock_Error_Min, 0x189C}, // DSP (0x189c): Phase Unlock Err Min = 6300
{DRC_Phase_Lock_Total_Error_Max_Ramp_Detector_Max, 0x3050}, // DSP (0x3050): Phase total err Ramp Max: Phase Tot Err Max = 80; Ramp Max = 48
// Defect_DVDG_Params
{Defect_Ctrl, 0x0004}, // DSP (0x0004): DRC defect use DRC equlalizer
{Defect_Peak_Time1, 0x0020}, // DSP (0x20)
{Defect_Peak_Time2, 0x0100}, // DSP (0x100)
{Srv_Defect_Peak_Time1, 0x0040}, // DSP (0x40)
{Srv_Defect_Peak_Time2, 0x0080}, // DSP (0x80)
{Defect_Parameters, 0x808A}, // DSP (0x808a): Defect Enable ; Defect Threshold = 0x28
{Defect_Delay, 0x0200}, // DSP (0x0200): Defect Delay = 0x200
{WD_Parameters, 0x0000}, // DSP (0x0000): Defect Enable ; Defect Threshold = 0x28
// AGC_DVDG_Params
{AGC_Params0, 0x0080}, // DSP (0x0080): peak detector window length (100 samples)
{AGC_Params1, 0x0080}, // DSP (0x0080): sat detector window length (100 samples)
{AGC_Params2, 0x1044}, // DSP (0x1044): acc.width (0x1), gain up (0x1) and down (0x4) steps
{AGC_Params3, 0x003C}, // DSP (0x003c): max of RF signal
{AGC_Params4, 0x0034}, // DSP (0x0034): min of RF signal
{AGC_Control, 0x2807}, // DSP (0x2807)
{DRC_Freq_Delta, 0x0098}, // DSP (0x0098): Freq Det Max Delta = 152
{DRC_Global_Programming, 0x0000}, // DSP (0x0000): Release DRC
{DRC_DPLL_Global_Programming, 0xF0C9}, // DSP (0xf0c9): DPLL: 'DVD'; Enable DPLL NB; elease DPLL; No Freeze; Lock Mode = Freq&Phase; Truncate PLL width; Time Out
{DRC_Defect_Programming, 0x0070}, // DSP (0x0070): enable freeze on defect for DPLL, Threshold & Viterbi; External defect active high; use internal defect
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDSLSParams[] = {
// Drc parameters for DVDSL
{Defect_Parameters, 0x8040}, // DSP (0x8040)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDDLSParams[] = {
// Drc parameters for DVDDL
{Defect_Parameters, 0x8040}, // DSP (0x8040)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDRSParams[] = {
// Drc parameters for DVDR
{Defect_Parameters, 0x8028}, // DSP (0x8028)
{DRC_DPLL_Filter_Wide_Band, 0x8840}, // DSP (0x8840)
{DRC_DPLL_Filter_Narrow_Band, 0x8840}, // DSP (0x8840)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDRWSParams[] = {
// Drc parameters for DVDRW
{Defect_Parameters, 0x8098}, // DSP (0x8098)
#ifdef DRV_DVDRW_WHITE_DOT_HANDLING
{Defect_Ctrl, 0x0008}, // DSP (0x0008)
#else
{Defect_Ctrl, 0x0000}, // DSP (0x0000)
#endif
{DRC_Infilter, 0x8000}, // DSP (0x8000)
{DRC_DPLL_Filter_Wide_Band, 0x6640}, // DSP (0x6640)
{DRC_DPLL_Filter_Narrow_Band, 0x6640}, // DSP (0x6640)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDRWEnableWhiteDotParams[] = {
{Defect_Ctrl, 0x0008}, // DSP (0x0008)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDRWDisableWhiteDotParams[] = {
{Defect_Ctrl, 0x0000}, // DSP (0x0000)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDLongDefectParams[] = {
{DRC_DPLL_Filter_Wide_Band, 0x8840}, // DSP (0x8840)
{DRC_DPLL_Filter_Narrow_Band, 0x8840}, // DSP (0x8840)
{Defect_Parameters, 0x8040}, // DSP (0x8040)
{DRC_Infilter, 0x0001}, // DSP (0x0001)
{DRC_Equalizer_HPF, 0x8A80}, // DSP (0x8a80)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDShortDefectParams[] = {
{DRC_DPLL_Filter_Wide_Band, 0x7740}, // DSP (0x7740)
{DRC_DPLL_Filter_Narrow_Band, 0x7740}, // DSP (0x7740)
{Defect_Parameters, 0x80A0}, // DSP (0x80a0)
{DRC_Infilter, 0x8000}, // DSP (0x8000)
{DRC_Equalizer_HPF, 0x8880}, // DSP (0x8880)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDRWLongDefectParams[] = {
{DRC_DPLL_Filter_Wide_Band, 0x8760}, // DSP (0x8760)
{DRC_DPLL_Filter_Narrow_Band, 0x8760}, // DSP (0x8760)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDRWShortDefectParams[] = {
{DRC_DPLL_Filter_Wide_Band, 0x6640}, // DSP (0x6640)
{DRC_DPLL_Filter_Narrow_Band, 0x6640}, // DSP (0x6640)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDRLongDefectParams[] = {
{Defect_Parameters, 0x8028}, // DSP (0x8028)
{DRC_Infilter, 0x0004}, // DSP (0x0004)
{DRC_Equalizer_HPF, 0x8A80}, // DSP (0x8a80)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDRShortDefectParams[] = {
{Defect_Parameters, 0x80C0}, // DSP (0x80c0)
{DRC_Infilter, 0x8000}, // DSP (0x8000)
{DRC_Equalizer_HPF, 0x8880}, // DSP (0x8880)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDDefaultReadParams[] = {
{0x0818, 0x001C}, // DSP (0x001c)
{0x0819, 0x00A4}, // DSP (0x00a4)
{0x0800, 0x0001}, // DSP (0x0001)
{0x0810, 0xF029}, // DSP (0xf029)
{0x0804, 0x8001}, // DSP (0x8001)
{0x0805, 0x8A80}, // DSP (0x8a80)
{0x0812, 0x7521}, // DSP (0x7521)
{0x0813, 0x8541}, // DSP (0x8541)
{0x0810, 0xF0C9}, // DSP (0xf0c9)
{0x0807, 0x0074}, // DSP (0x0074)
{0x0803, 0x0080}, // DSP (0x0080)
{0x0800, 0x0000}, // DSP (0x0000)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDNbcaReadParams[] = {
{0x0800, 0x0001}, // DSP (0x0001)
{0x0810, 0xF129}, // DSP (0xf129)
{0x0804, 0x8000}, // DSP (0x8000)
{0x0805, 0x0A80}, // DSP (0x0a80)
{0x0812, 0x7520}, // DSP (0x7520)
{0x0813, 0x7540}, // DSP (0x7540)
{0x0810, 0xF1D9}, // DSP (0xf1d9)
{0x0807, 0x0000}, // DSP (0x0000)
{0x0803, 0x8040}, // DSP (0x8040)
{0x0800, 0x0020}, // DSP (0x0020)
PARAMS_TERMINATOR
};
CONST DrcParam DrcDVDDefaultSearchParams[] = {
{0xa03, 0x4A43}, // DSP (0x4a43): set RF channel resistance to 10kohm
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