/**********************************************************************************
 *  Copyright (c) 2001 ZORAN Corporation, All Rights Reserved
 *  THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF ZORAN CORPORATION
 *
 *  File: "DrcParams.h"
 *
 * Description:
 * ============
 * CPU<->DRC Interface
 * 
 * Log:
 * ====
 * $Revision: $
 * Last Modified by $Author: $ at $Modtime: $ 
 **********************************************************************************
 * Updates:
 **********************************************************************************
 * $Log: 
 * 
 * 
 *********************************************************************************/
#include "Config.h"		/* Global Configuration - do not remove! */


#ifndef _FE_DRC_PARAMS_H
#define _FE_DRC_PARAMS_H


// DRC - Loop Global Programming
#define DRC_Global_Programming			0x800
#define DRC_Equalizer_Programming		0x801
#define DRC_Threshold_Programming		0x802
#define DRC_Threshold_Fix_Value			0x803
#define DRC_Infilter					0x804
#define DRC_Equalizer_HPF				0x805
#define DRC_Defect_Programming			0x807
#define DRC_Coef0817_Programming		0x808
#define DRC_Coef2635_Programming		0x809
#define DRC_Coef4_Programming			0x80a

// DRC - DPLL Programming
#define DRC_DPLL_Global_Programming		0x810
#define DRC_DPLL_Filter_Wide_Band		0x812
#define DRC_DPLL_Filter_Narrow_Band		0x813
#define DRC_DPLL_Filter_Minimum_Width	0x815
#define DRC_DPLL_Invalid_Sync			0x817
#define DRC_DPLL_Freq_Ratio_Initial_Value_MSB	0x818
#define DRC_DPLL_Freq_Ratio_Initial_Value_LSB	0x819
#define DRC_DPLL_Number_Of_Good_Frame_For_NB	0x81a
#define DRC_DPLL_Frame_Window					0x81b
#define DRC_DPLL_Freq_Ratio_Current_Value_MSB	0x81c
#define DRC_DPLL_Freq_Ratio_Current_Value_LSB	0x81d
#define DRC_DPLL_Status					0x81e
#define DRC_DPLL_Pll_Counter			0x81f

// DRC - Phase Detector Programming
#define DRC_Phase_Lock_Error_Init		0x820
#define DRC_Phase_Lock_Total_Error_Max_Ramp_Detector_Max	0x821
#define DRC_Phase_Lock_Error_Min		0x823
#define DRC_Phase_Unlock_Error_Max		0x824

// DRC - Viterbi Programming
#define DRC_Viterbi_Peak_Init			0x828
#define DRC_Viterbi_Peak_Limiter_And_Memory_Depth	0x829
#define DRC_Viterbi_Const___01_16__2_5__10_07		0x82a
#define DRC_Viterbi_Const_11_06__3_4				0x82b
#define DRC_Viterbi_Posneg_Peak_Readback			0x82c
#define DRC_Viterbi_Const16_5_7			0x82d
#define DRC_Viterbi_Const6_4_Pit		0x82e

// DRC - Frequency Detector  Programming
#define DRC_Freq_Samples_Per_Window_Frame		0x830
#define DRC_Freq_Detector_Status		0x831
#define DRC_Freq_Delta					0x832
#define DRC_Freq_Detector_Global_Parameters		0x835
#define DRC_Freq_Sync_Delta				0x836
#define DRC_Freq_Irq_Status				0x837

// DRC accumulator
#define DRC_Accumulator					0x870

// DRC - AGC Programming
#define AGC_Window_Size					0x882

// ADC At speed Min/Max

// DRC - ADC Programming
#define ADC_Dig_Offset_RF				0x890
#define ADC_Dig_Offset_RF_Shadow        0x408e

// DRC - At Speed Programming
#define ADC_At_Speed_Fifo_LSB			0x8b0
#define ADC_At_Speed_Fifo_MSB			0x8b1
#define ADC_At_Speed_Mode				0x8b2
#define ADC_At_Speed_Status				0x8b3
#define ADC_At_Speed_Prog_Status		0x8b4

// DRC - Jitter Meter Programming
#define Jitter_Meter_Start_Stop			0x8c0
#define Jitter_Meter_Mode				0x8c1
#define Jitter_Meter_Alpha				0x8c2
//#define Jitter_Meter_Win_Peak			0x8c3
//#define Jitter_Meter_Variance			0x8c4
#define Jitter_Meter_Window				0x8c5
#define Jitter_Meter_Inputs_And_Result	0x8c7

// DRC - DRC Global Programming
#define DRC_Init						0x8e1
#define DRC_Interrupt_Masker			0x8e2
#define DRC_Interrupt_Induction			0x8e3
#define DRC_Unmasked_Interrupt_Request	0x8e4
#define DRC_Clock_Enable				0x8e8

// AFE top
#define AFE_Init						0xa00
#define KARAOKE_Pwr_Dn					0xa01
#define AFE_Pwr_Dn						0xa02
#define AFE_Ctrl						0xa03
#define RF_Ofst							0xa05
#define ALPC_Gain						0xa06
#define Mon_Sel							0xa07
//#define AFE_Tune						0xa08
#define Byp_Sel							0xa09
#define Sfrwq_Set						0xa0a
#define Comp_Ctrl                       0xa0b

// Karaoke 
#define Karaoke_Params                  0xa0c
#define Karaoke_Seed                    0xa0d
#define Karaoke_Cic_Params              0xa0e
#define Karaoke_Data                    0xa0f

// AFE control
#define Sample_Ctrl1					0xa10
#define Sample_Ctrl2					0xa11
#define	Sample_Ctrl3					0xa12
#define	Sample_Ctrl4					0xa13
#define	Reg_G				    		0xa14
#define	Reg_H			        		0xa15

// AGC
#define AGC_Params0						0xa40
#define AGC_Params1 					0xa41
#define AGC_Params2						0xa42
#define AGC_Params3 					0xa43
#define AGC_Params4		 				0xa44
#define AGC_Control 					0xa45
#define AGC_Status0 					0xa46
#define AGC_Status1						0xa47
#define AGC_Status2			 			0xa48
#define AGC_Status3			 			0xa49
#define AGC_Status4						0xa4a
#define	AgcControlShadow				0x8054

// AMTR
#define AMTR_Contro0					0xa50
#define AMTR_Control1					0xa51
#define AMTR_Control2					0xa52
#define AMTR_Status						0xa53
#define AMTR_Channel0					0xa54
#define AMTR_Channel1					0xa55
#define AMTR_Channel2					0xa56
#define AMTR_Channel3					0xa57

// DPD
#define DPD_Control						0xa70
#define DPD_Params0						0xa71
//#define DPD_Params1						0xa72
//#define DPD_Params2						0xa73

// Defect
#define Defect_Ctrl						0xa80
#define Defect_Peak_Time				0xa81
#define Defect_Parameters				0xa82
#define Defect_Delay					0xa83
#define WD_Parameters					0xa84
#define Srv_Defect_Parameters			0xa85
#define Srv_Defect_Delay				0xa86
#define Srv_WD_Parameters				0xa87
#define Mirr_Defect_Parameters			0xa88
#define Defect_Top_Filtered				0xa89
#define Defect_Bottom_Filtered			0xa8a
#define Srv_BD_Th1						0xa8b
#define Drc_BD_Th1                      0xa8c
#define Mirr_Th1                        0xa8d
#define Drc_WD_Th1                      0xa8e
#define Defect_Status					0xa8f
#define Defect_Peak_Time1				0xa90
#define Defect_Peak_Time2				0xa91
#define Srv_Defect_Peak_Time1			0xa92
#define Srv_Defect_Peak_Time2			0xa93
#define Srv_Top_Filtered				0xa94
#define Srv_Bottom_Filtered				0xa95


#endif