//File named C6xdsp.h

/*******************************************************************************
* FILENAME
*   c641x.h
*
* DESCRIPTION
*   c641x Header File
*
*******************************************************************************/

/* Register definitions for C641x chip */

/* Define EMIF Registers  */
#define EMIFA_GCTL       0x01800000  //全局控制寄存器  GBLCTL
#define EMIFA_CE1        0x01800004  //CE1控制寄存器   CE1CTL
#define EMIFA_CE0        0x01800008  //                CE0CTL
#define EMIFA_CE2        0x01800010  //                CE2CTL
#define EMIFA_CE3        0x01800014  //                CE3CTL
#define EMIFA_SDRAMCTL   0x01800018  //SDRAM控制寄存器       SDCTL
#define EMIFA_SDRAMREF   0x0180001c  //SDRAM時(shí)許序控制寄存器 SDTIM
#define EMIFA_SDRAMEXT   0x01800020  //SDRAM擴(kuò)展控制寄存器   SDEXT
#define EMIFA_CE1SECCTL  0x01800044  //CE1第二控制寄存器     CE1SEC
#define EMIFA_CE0SECCTL  0x01800048  // 					 CE0SEC
#define EMIFA_CE2SECCTL  0x01800050  //						 CE2SEC
#define EMIFA_CE3SECCTL  0x01800054  //						 CE3SEC

#define EMIFB_GCTL       0x01A80000
#define EMIFB_CE1        0x01A80004
#define EMIFB_CE0        0x01A80008
#define EMIFB_CE2        0x01A80010
#define EMIFB_CE3        0x01A80014
#define EMIFB_SDRAMCTL   0x01A80018
#define EMIFB_SDRAMREF   0x01A8001c
#define EMIFB_SDRAMEXT   0x01A80020
#define EMIFB_CE1SECCTL  0x01A80044
#define EMIFB_CE0SECCTL  0x01A80048
#define EMIFB_CE2SECCTL  0x01A80050
#define EMIFB_CE3SECCTL  0x01A80054
 
/* Define McBSP0 Registers */
#define McBSP0_DRR      0x018c0000   /* Address of data receive reg.         */
#define McBSP0_DXR      0x018c0004   /* Address of data transmit reg.        */
#define McBSP0_SPCR     0x018c0008   /* Address of serial port contl. reg.   */
#define McBSP0_RCR      0x018c000C   /* Address of receive control reg.      */
#define McBSP0_XCR      0x018c0010   /* Address of transmit control reg.     */
#define McBSP0_SRGR     0x018c0014   /* Address of sample rate generator     */
#define McBSP0_MCR      0x018c0018   /* Address of multichannel reg.         */
#define McBSP0_RCER     0x018c001C   /* Address of receive channel enable.   */
#define McBSP0_XCER     0x018c0020   /* Address of transmit channel enable.  */
#define McBSP0_PCR      0x018c0024   /* Address of pin control reg.          */

/* Define McBSP1 Registers */
#define McBSP1_DRR      0x1900000   /* Address of data receive reg.         */
#define McBSP1_DXR      0x1900004   /* Address of data transmit reg.        */
#define McBSP1_SPCR     0x1900008   /* Address of serial port contl. reg.   */
#define McBSP1_RCR      0x190000C   /* Address of receive control reg.      */
#define McBSP1_XCR      0x1900010   /* Address of transmit control reg.     */
#define McBSP1_SRGR     0x1900014   /* Address of sample rate generator     */
#define McBSP1_MCR      0x1900018   /* Address of multichannel reg.         */
#define McBSP1_RCER     0x190001C   /* Address of receive channel enable.   */
#define McBSP1_XCER     0x1900020   /* Address of transmit channel enable.  */
#define McBSP1_PCR      0x1900024   /* Address of pin control reg.          */

/* Define McBSP2 Registers */
#define McBSP2_DRR      0x1A40000   /* Address of data receive reg.         */
#define McBSP2_DXR      0x1A40004   /* Address of data transmit reg.        */
#define McBSP2_SPCR     0x1A40008   /* Address of serial port contl. reg.   */
#define McBSP2_RCR      0x1A4000C   /* Address of receive control reg.      */
#define McBSP2_XCR      0x1A40010   /* Address of transmit control reg.     */
#define McBSP2_SRGR     0x1A40014   /* Address of sample rate generator     */
#define McBSP2_MCR      0x1A40018   /* Address of multichannel reg.         */
#define McBSP2_RCER     0x1A4001C   /* Address of receive channel enable.   */
#define McBSP2_XCER     0x1A40020   /* Address of transmit channel enable.  */
#define McBSP2_PCR      0x1A40024   /* Address of pin control reg.          */

/* Define L2 Cache Registers */
#define L2CFG           0x1840000   /* Address of L2 config reg             */
#define MAR0            0x1848200   /* Address of mem attribute reg         */

/* Define Interrupt Registers */
#define MUXH            0x19c0000   /* Address of Interrupt Multiplexer High*/
#define MUXL            0x19c0004   /* Address of Interrupt Multiplexer Low */
#define EXTPOL          0x19c0008   /* Address of External Interrupt Polarity */

/* Define Timer0 Registers */
#define TIMER0_CTRL     0x1940000	/* Address of timer0 control reg.       */
#define TIMER0_PRD      0x1940004	/* Address of timer0 period reg.        */
#define TIMER0_COUNT    0x1940008	/* Address of timer0 counter reg.       */

/* Define Timer1 Registers */
#define TIMER1_CTRL     0x1980000	/* Address of timer1 control reg.       */
#define TIMER1_PRD      0x1980004	/* Address of timer1 period reg.        */
#define TIMER1_COUNT    0x1980008	/* Address of timer1 counter reg.       */

/* Define Timer1 Registers */
#define TIMER2_CTRL     0x1AC0000	/* Address of timer1 control reg.       */
#define TIMER2_PRD      0x1AC0004	/* Address of timer1 period reg.        */
#define TIMER2_COUNT    0x1AC0008	/* Address of timer1 counter reg.       */


/* Define DMA Registers */  

/* channel 0 */
//#define PRICTL0			0x1840000   /* DMA channel primary control register 0 */
//#define SECCTL0			0x1840008   /* DMA channel secondary control register 0 */
//#define SRC0			0x1840010   /* DMA channel source address register 0 */
//#define	DST0			0x1840018   /* DMA channel destination address register 0*/
//#define XFRCNT0			0x1840020   /* DMA channel transfer counter register 0 */
/* channel 1 */ 
//#define PRICTL1			0x1840040   /* DMA channel primary control register 1 */
//#define SECCTL1			0x1840048   /* DMA channel secondary control register 1 */
//#define SRC1			0x1840050   /* DMA channel source address register 1 */
//#define	DST1			0x1840058   /* DMA channel destination address register 1 */
//#define XFRCNT1			0x1840060   /* DMA channel transfer counter register 1 */
/* channel 2 */
//#define PRICTL2			0x1840004   /* DMA channel primary control register 2 */
//#define SECCTL2			0x184000C   /* DMA channel secondary control register 2 */
//#define SRC2			0x1840014   /* DMA channel source address register 2 */
//#define	DST2			0x184001C   /* DMA channel destination address register 2 */
//#define XFRCNT2			0x1840024   /* DMA channel transfer counter register 2 */
/* channel 3 */
//#define PRICTL3			0x1840044   /* DMA channel primary control register 3 */
//#define SECCTL3			0x184004C   /* DMA channel secondary control register 3 */
//#define SRC3			0x1840054   /* DMA channel source address register 3 */
//#define	DST3			0x184005C   /* DMA channel destination address register 3 */
//#define XFRCNT3			0x1840064   /* DMA channel transfer counter register 3 */

//#define GBLCNTA			0x1840028   /* DMA global count reload register A */
//#define GBLIDXA			0x1840030   /* DMA global index register A  */

//#define GBLCNTB			0x184002C   /* DMA global count reload register B */
//#define GBLIDXB			0x1840034   /* DMA global index register B  */

//#define GBLADDRA		0x1840038   /* DMA global address register A */
//#define GBLADDRB		0x184003C   /* DMA global address register B */
//#define GBLADDRC		0x1840068   /* DMA global address register C */
//#define GBLADDRD		0x184006C   /* DMA global address register D */

//#define AUXCTL			0x1840070   /* DMA auxiliary control register */

/* Define EDMA Registers */
#define PQSR			0x01A0FFE0	/* Address of priority queue status     */
#define CIPR			0x01A0FFE4	/* Address of channel interrupt pending */
#define CIER			0x01A0FFE8	/* Address of channel interrupt enable  */
#define CCER			0x01A0FFEC	/* Address of channel chain enable      */
#define ER				0x01A0FFF0	/* Address of event register            */
#define EER				0x01A0FFF4	/* Address of event enable register     */
#define ECR				0x01A0FFF8	/* Address of event clear register      */
#define ESR				0x01A0FFFC	/* Address of event set register        */

/* Define EDMA Transfer Parameter Entry Fields */
#define OPT				0*4			/* Options Parameter                    */
#define SRC				1*4			/* SRC Address Parameter                */
#define CNT				2*4			/* Count Parameter                      */
#define DST				3*4			/* DST Address Parameter                */
#define IDX				4*4			/* IDX Parameter                        */
#define LNK				5*4			/* LNK Parameter                        */
						
/* Define EDMA Parameter RAM Addresses */ 
#define EVENT0_PARAMS 0x01A00000
#define EVENT1_PARAMS EVENT0_PARAMS + 0x18
#define EVENT2_PARAMS EVENT1_PARAMS + 0x18
#define EVENT3_PARAMS EVENT2_PARAMS + 0x18
#define EVENT4_PARAMS EVENT3_PARAMS + 0x18
#define EVENT5_PARAMS EVENT4_PARAMS + 0x18
#define EVENT6_PARAMS EVENT5_PARAMS + 0x18
#define EVENT7_PARAMS EVENT6_PARAMS + 0x18
#define EVENT8_PARAMS EVENT7_PARAMS + 0x18
#define EVENT9_PARAMS EVENT8_PARAMS + 0x18
#define EVENTA_PARAMS EVENT9_PARAMS + 0x18
#define EVENTB_PARAMS EVENTA_PARAMS + 0x18
#define EVENTC_PARAMS EVENTB_PARAMS + 0x18
#define EVENTD_PARAMS EVENTC_PARAMS + 0x18
#define EVENTE_PARAMS EVENTD_PARAMS + 0x18
#define EVENTF_PARAMS EVENTE_PARAMS + 0x18
#define EVENTN_PARAMS EVENTF_PARAMS + 0x18
#define EVENTO_PARAMS EVENTN_PARAMS + 0x18
#define EVENT24_PARAMS EVENT0_PARAMS + 0x18*24
//#define EVENT25_PARAMS EVENT0_PARAMS + 0x18*24
#define EVENT25_PARAMS EVENT0_PARAMS + 0x18*25

#define  EVENT24L_PARAMS   0x01A00600             /* EDMA OPTIONS REGISTER */
#define  EVENT25L_PARAMS   0x01A00618             /* EDMA OPTIONS REGISTER */

/* Define QDMA Memory Mapped Registers */
#define QDMA_OPT		0x02000000	/* Address of QDMA options register     */
#define QDMA_SRC		0x02000004	/* Address of QDMA SRC address register */
#define QDMA_CNT		0x02000008	/* Address of QDMA counts register      */
#define QDMA_DST		0x0200000C	/* Address of QDMA DST address register */
#define QDMA_IDX		0x02000010	/* Address of QDMA index register       */
 
/* Define QDMA Pseudo Registers */
#define QDMA_S_OPT		0x02000020	/* Address of QDMA options register     */
#define QDMA_S_SRC		0x02000024	/* Address of QDMA SRC address register */
#define QDMA_S_CNT		0x02000028	/* Address of QDMA counts register      */
#define QDMA_S_DST		0x0200002C	/* Address of QDMA DST address register */
#define QDMA_S_IDX		0x02000030	/* Address of QDMA index register       */

/* Definitions for the DSK Board and SW */
#define PI				3.1415926
#define IO_PORT			0x90080000  /* I/O port Address,top byte valid data */
#define INTERNAL_MEM_SIZE (0x3000)>>2
#define EXTERNAL_MEM_SIZE (0x400000)>>2
#define FLASH_SIZE		0x20000 
#define POST_SIZE		0x10000 
#define FLASH_WRITE_SIZE 0x80 
#define INTERNAL_MEM_START 0xD000
#define EXTERNAL_MEM_START 0x80000000
#define FLASH_START		0x90000000
#define POST_END		0x90010000 
#define FLASH_ADR1		0x90005555
#define FLASH_ADR2		0x90002AAA
#define FLASH_KEY1		0xAA
#define FLASH_KEY2		0x55
#define FLASH_KEY3		0xA0
#define ALL_A			0xaaaaaaaa
#define ALL_5			0x55555555
#define ALT_A5			0xa5a5a5a5
#define ALT_5A			0x5a5a5a5a
#define CE1_8			0xffffff03  /* reg to set CE1 as 8bit async */
#define CE1_32			0xffffff23  /* reg to set CE1 as 32bit async */