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<title>Hardware API Selector: AT91SAM7SE512 Definitions</title>
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<h1>Static Memory Controller 2 Interface Peripheral</h1>
<null><a name="SMC"></a><b>SMC</b> <i><font size="-1">(<a href="AT91SAM7SE512_h.html#AT91S_SMC2">AT91S_SMC2</a>)</font></i><b> 0xFFFFFF90 </b><i><font size="-1">(<a href="AT91SAM7SE512_h.html#AT91C_BASE_SMC">AT91C_BASE_SMC</a>)</font></i>
<br></null><a name="SMC2"></a><h2>SMC2 Software API <i><font size="-1">(<a href="AT91SAM7SE512_h.html#AT91S_SMC2">AT91S_SMC2</a>)</font></i></h2>
<a name="SMC2"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1">SMC2_CSR[8] (<a href="AT91SAM7SE512_SMC2.html#SMC2_CSR">SMC2_CSR</a>)</font></td><td><font size="-1">SMC2 Chip Select Register</font></td></tr>
</null></table><br></null><h2>SMC2 Register Description</h2>
<null><a name="SMC2_CSR"></a><h4><a href="#SMC2">SMC2</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> SMC2_CSR <i>SMC2 Chip Select Register</i></h4><ul><null><font size="-2"><li><b>SMC</b> <i><a href="AT91SAM7SE512_h.html#AT91C_SMC_CSR">AT91C_SMC_CSR</a></i> 0xFFFFFF90</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">6..0</td><td align="CENTER"><a name="SMC2_NWS"></a><b>SMC2_NWS</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_NWS">AT91C_SMC2_NWS</a></font></td><td><b>Number of Wait States</b><br>This field defines the Read and Write signal pulse length from 1 cycle up to 128 cycles.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SMC2_WSEN"></a><b>SMC2_WSEN</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_WSEN">AT91C_SMC2_WSEN</a></font></td><td><b>Wait State Enable</b><br>0 = Wait States are disabled.<br>1 = Wait States are enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..8</td><td align="CENTER"><a name="SMC2_TDF"></a><b>SMC2_TDF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_TDF">AT91C_SMC2_TDF</a></font></td><td><b>Data Float Time</b><br>The external bus is marked occupied and cannot be used by another chip select during TDF cycle.<br>Up to 15 cycles can be defined.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="SMC2_BAT"></a><b>SMC2_BAT</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_BAT">AT91C_SMC2_BAT</a></font></td><td><b>Byte Access Type</b><br>This field is used only if DBW defines a 16- or 32-bit data bus.<br>0 = Chip Select line is connected to two 8-bit wide devices or four 8-bit devices.<br>1 = Chip Select line is connected to a 16-bit wide device.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="SMC2_DBW"></a><b>SMC2_DBW</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_DBW">AT91C_SMC2_DBW</a></font></td><td><b>Data Bus Width</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">1</td><td align="CENTER"><a name="SMC2_DBW_16"></a><b>SMC2_DBW_16</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_DBW_16">AT91C_SMC2_DBW_16</a></font></td><td><br>16-bit.</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SMC2_DBW_8"></a><b>SMC2_DBW_8</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_DBW_8">AT91C_SMC2_DBW_8</a></font></td><td><br>8-bit.</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">15</td><td align="CENTER"><a name="SMC2_DRP"></a><b>SMC2_DRP</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_DRP">AT91C_SMC2_DRP</a></font></td><td><b>Data Read Protocol</b><br>0 = Standard Read Protocol is used.<br>1 = Early Read Protocol is used.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17..16</td><td align="CENTER"><a name="SMC2_ACSS"></a><b>SMC2_ACSS</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_ACSS">AT91C_SMC2_ACSS</a></font></td><td><b>Address to Chip Select Setup</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SMC2_ACSS_STANDARD"></a><b>SMC2_ACSS_STANDARD</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_ACSS_STANDARD">AT91C_SMC2_ACSS_STANDARD</a></font></td><td><br>Standard, asserted at the beginning of the access and deasserted at the end.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SMC2_ACSS_1_CYCLE"></a><b>SMC2_ACSS_1_CYCLE</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_ACSS_1_CYCLE">AT91C_SMC2_ACSS_1_CYCLE</a></font></td><td><br>One cycle less at the beginning and the end of the access.</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SMC2_ACSS_2_CYCLES"></a><b>SMC2_ACSS_2_CYCLES</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_ACSS_2_CYCLES">AT91C_SMC2_ACSS_2_CYCLES</a></font></td><td><br>Two cycles less at the beginning and the end of the access.</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SMC2_ACSS_3_CYCLES"></a><b>SMC2_ACSS_3_CYCLES</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_ACSS_3_CYCLES">AT91C_SMC2_ACSS_3_CYCLES</a></font></td><td><br>Three cycles less at the beginning and the end of the access.</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">26..24</td><td align="CENTER"><a name="SMC2_RWSETUP"></a><b>SMC2_RWSETUP</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_RWSETUP">AT91C_SMC2_RWSETUP</a></font></td><td><b>Read and Write Signal Setup Time</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">30..28</td><td align="CENTER"><a name="SMC2_RWHOLD"></a><b>SMC2_RWHOLD</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SMC2_RWHOLD">AT91C_SMC2_RWHOLD</a></font></td><td><b>Read and Write Signal Hold Time</b></td></tr>
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