<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x120</b></font></td><td><font size="-1">TWI_PTCR (<a href="AT91SAM7SE512_PDC.html#PDC_PTCR">PDC_PTCR</a>)</font></td><td><font size="-1">PDC Transfer Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x124</b></font></td><td><font size="-1">TWI_PTSR (<a href="AT91SAM7SE512_PDC.html#PDC_PTSR">PDC_PTSR</a>)</font></td><td><font size="-1">PDC Transfer Status Register</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7SE512_h.html#AT91F_TWI_EnableIt">AT91F_TWI_EnableIt</a></b></font></td><td><font size="-1">Enable TWI IT</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7SE512_h.html#AT91F_TWI_DisableIt">AT91F_TWI_DisableIt</a></b></font></td><td><font size="-1">Disable TWI IT</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7SE512_h.html#AT91F_TWI_GetInterruptMaskStatus">AT91F_TWI_GetInterruptMaskStatus</a></b></font></td><td><font size="-1">Return TWI Interrupt Mask Status</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7SE512_h.html#AT91F_TWI_IsInterruptMasked">AT91F_TWI_IsInterruptMasked</a></b></font></td><td><font size="-1">Test if TWI Interrupt is Masked </font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7SE512_h.html#AT91F_TWI_Configure">AT91F_TWI_Configure</a></b></font></td><td><font size="-1">Configure TWI in master mode</font></td></tr>
</null></table></null><h2>TWI Register Description</h2>
<null><a name="TWI_CR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> TWI_CR  <i>Control Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7SE512_h.html#AT91C_TWI_CR">AT91C_TWI_CR</a></i> 0xFFFB8000</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TWI_START"></a><b>TWI_START</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_START">AT91C_TWI_START</a></font></td><td><b>Send a START Condition</b><br>0: No effect.<br>1: A frame beginning with a START bit is transmitted according to the features defined in the mode register.<br>This action is necessary when the TWI peripheral wants to read data from a slave. When configured in master mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TWI_STOP"></a><b>TWI_STOP</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_STOP">AT91C_TWI_STOP</a></font></td><td><b>Send a STOP Condition</b><br>0: No effect.<br>1: STOP Condition is sent just after completing the current byte transmission in master read or write mode.<br>In single data byte master read or write, the START and STOP must both be set.<br>In multiple data bytes master read or write, the STOP must be set before ACK/NACK bit transmission.<br>In master read mode, if a NACK bit is received, the STOP is automatically performed.<br>In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TWI_MSEN"></a><b>TWI_MSEN</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_MSEN">AT91C_TWI_MSEN</a></font></td><td><b>TWI Master Transfer Enabled</b><br>0: No effect.<br>1: If MSDIS = 0, the master data transfer is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TWI_MSDIS"></a><b>TWI_MSDIS</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_MSDIS">AT91C_TWI_MSDIS</a></font></td><td><b>TWI Master Transfer Disabled</b><br>0: No effect.<br>1: The master data transfer is disabled, all pending data is transmitted. The shifter and holding character (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="TWI_SVEN"></a><b>TWI_SVEN</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_SVEN">AT91C_TWI_SVEN</a></font></td><td><b>TWI Slave mode Enabled</b><br>0: No effect.<br>1: If SVEN = 1, the slave mode is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="TWI_SVDIS"></a><b>TWI_SVDIS</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_SVDIS">AT91C_TWI_SVDIS</a></font></td><td><b>TWI Slave mode Disabled</b><br>0: No effect.<br>1: If SVDIS = 1, The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TWI_SWRST"></a><b>TWI_SWRST</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_SWRST">AT91C_TWI_SWRST</a></font></td><td><b>Software Reset</b><br>0: No effect.<br>1: Equivalent to a system reset.</td></tr>
</null></table>
<a name="TWI_MMR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> TWI_MMR  <i>Master Mode Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7SE512_h.html#AT91C_TWI_MMR">AT91C_TWI_MMR</a></i> 0xFFFB8004</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..8</td><td align="CENTER"><a name="TWI_IADRSZ"></a><b>TWI_IADRSZ</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_IADRSZ">AT91C_TWI_IADRSZ</a></font></td><td><b>Internal Device Address Size</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="TWI_IADRSZ_NO"></a><b>TWI_IADRSZ_NO</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_IADRSZ_NO">AT91C_TWI_IADRSZ_NO</a></font></td><td><br>No internal device address</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="TWI_IADRSZ_1_BYTE"></a><b>TWI_IADRSZ_1_BYTE</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_IADRSZ_1_BYTE">AT91C_TWI_IADRSZ_1_BYTE</a></font></td><td><br>One-byte internal device address</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="TWI_IADRSZ_2_BYTE"></a><b>TWI_IADRSZ_2_BYTE</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_IADRSZ_2_BYTE">AT91C_TWI_IADRSZ_2_BYTE</a></font></td><td><br>Two-byte internal device address</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="TWI_IADRSZ_3_BYTE"></a><b>TWI_IADRSZ_3_BYTE</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_IADRSZ_3_BYTE">AT91C_TWI_IADRSZ_3_BYTE</a></font></td><td><br>Three-byte internal device address</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="TWI_MREAD"></a><b>TWI_MREAD</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_MREAD">AT91C_TWI_MREAD</a></font></td><td><b>Master Read Direction</b><br>0: Master write direction<br>1: Master read direction</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">22..16</td><td align="CENTER"><a name="TWI_DADR"></a><b>TWI_DADR</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_DADR">AT91C_TWI_DADR</a></font></td><td><b>Device Address</b><br>The device address is used in master mode to access slave devices in read or write mode.</td></tr>
</null></table>
<a name="TWI_SMR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> TWI_SMR  <i>Slave Mode Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7SE512_h.html#AT91C_TWI_SMR">AT91C_TWI_SMR</a></i> 0xFFFB8008</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">22..16</td><td align="CENTER"><a name="TWI_SADR"></a><b>TWI_SADR</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_SADR">AT91C_TWI_SADR</a></font></td><td><b>Slave Address</b><br>The slave device address is used in order to be accessed by master devices in read or write mode. SADR has to be programmed before enabling the Slave mode or after a general call.</td></tr>
</null></table>
<a name="TWI_IADR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> TWI_IADR  <i>Internal Address Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7SE512_h.html#AT91C_TWI_IADR">AT91C_TWI_IADR</a></i> 0xFFFB800C</font></null></ul><br>0, 1, 2 or 3 bytes depending on IADRSZ<a name="TWI_CWGR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> TWI_CWGR  <i>Clock Waveform Generator Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7SE512_h.html#AT91C_TWI_CWGR">AT91C_TWI_CWGR</a></i> 0xFFFB8010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="TWI_CLDIV"></a><b>TWI_CLDIV</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_CLDIV">AT91C_TWI_CLDIV</a></font></td><td><b>Clock Low Divider</b><br>The SCL low period is defined as follows: Tlow = (CLDIV * 2 ^CKDIV) + 4) * Tmclk</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..8</td><td align="CENTER"><a name="TWI_CHDIV"></a><b>TWI_CHDIV</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_CHDIV">AT91C_TWI_CHDIV</a></font></td><td><b>Clock High Divider</b><br>The SCL high period is defined as follows: Thigh = (CLDIV * 2 ^CKDIV) + 4) * Tmclk</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18..16</td><td align="CENTER"><a name="TWI_CKDIV"></a><b>TWI_CKDIV</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_CKDIV">AT91C_TWI_CKDIV</a></font></td><td><b>Clock Divider</b><br>The CKDIV is used to increase both SCL high and low periods.</td></tr>
</null></table>
<a name="TWI_SR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> TWI_SR  <i>Status Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7SE512_h.html#AT91C_TWI_SR">AT91C_TWI_SR</a></i> 0xFFFB8020</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0 slave</td><td align="CENTER"><a name="TWI_TXCOMP_SLAVE"></a><b>TWI_TXCOMP_SLAVE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_TXCOMP_SLAVE">AT91C_TWI_TXCOMP_SLAVE</a></font></td><td><b>Transmission Completed</b><br>0: As soon as a Start is detected.<br>1: After a Stop or a Repeated Start + an address different from SADR is detected.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1 slave</td><td align="CENTER"><a name="TWI_RXRDY"></a><b>TWI_RXRDY</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_RXRDY">AT91C_TWI_RXRDY</a></font></td><td><b>Receive holding register ReaDY</b><br>0: No character has been received since the last TWI_RHR read operation.<br>1: A byte has been received in the TWI_RHR since the last read.</td></tr>