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<h1>Clock Generator Controler Peripheral</h1>
<null><a name="CKGR"></a><b>CKGR</b> <i><font size="-1">(<a href="AT91SAM7SE512_h.html#AT91S_CKGR">AT91S_CKGR</a>)</font></i><b> 0xFFFFFC20 </b><i><font size="-1">(<a href="AT91SAM7SE512_h.html#AT91C_BASE_CKGR">AT91C_BASE_CKGR</a>)</font></i>
<br></null><a name="CKGR"></a><h2>CKGR Software API <i><font size="-1">(<a href="AT91SAM7SE512_h.html#AT91S_CKGR">AT91S_CKGR</a>)</font></i></h2>
<a name="CKGR"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1"><a href="AT91SAM7SE512_CKGR.html#CKGR_MOR">CKGR_MOR</a></font></td><td><font size="-1">Main Oscillator Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4</b></font></td><td><font size="-1"><a href="AT91SAM7SE512_CKGR.html#CKGR_MCFR">CKGR_MCFR</a></font></td><td><font size="-1">Main Clock Frequency Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xC</b></font></td><td><font size="-1"><a href="AT91SAM7SE512_CKGR.html#CKGR_PLLR">CKGR_PLLR</a></font></td><td><font size="-1">PLL Register</font></td></tr>
</null></table><br></null><h2>CKGR Register Description</h2>
<null><a name="CKGR_MOR"></a><h4><a href="#CKGR">CKGR</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> CKGR_MOR <i>Main Oscillator Register</i></h4><ul><null><font size="-2"><li><b>CKGR</b> <i><a href="AT91SAM7SE512_h.html#AT91C_CKGR_MOR">AT91C_CKGR_MOR</a></i> 0xFFFFFC20</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="CKGR_MOSCEN"></a><b>CKGR_MOSCEN</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_MOSCEN">AT91C_CKGR_MOSCEN</a></font></td><td><b>Main Oscillator Enable</b><br>0 = The main oscillator is disabled.<br>1 = The main oscillator is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="CKGR_OSCBYPASS"></a><b>CKGR_OSCBYPASS</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_OSCBYPASS">AT91C_CKGR_OSCBYPASS</a></font></td><td><b>Main Oscillator Bypass</b><br>0 = The main oscillator is not bypassed.<br>1 = The main oscillator is bypassed. MOSCEN bit must be set to 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..8</td><td align="CENTER"><a name="CKGR_OSCOUNT"></a><b>CKGR_OSCOUNT</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_OSCOUNT">AT91C_CKGR_OSCOUNT</a></font></td><td><b>Main Oscillator Start-up Time</b><br>Specifies the number of slow clock cycles multiplied by 8 for the main oscillator start-up time.</td></tr>
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<a name="CKGR_MCFR"></a><h4><a href="#CKGR">CKGR</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> CKGR_MCFR <i>Main Clock Frequency Register</i></h4><ul><null><font size="-2"><li><b>CKGR</b> <i><a href="AT91SAM7SE512_h.html#AT91C_CKGR_MCFR">AT91C_CKGR_MCFR</a></i> 0xFFFFFC24</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">15..0</td><td align="CENTER"><a name="CKGR_MAINF"></a><b>CKGR_MAINF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_MAINF">AT91C_CKGR_MAINF</a></font></td><td><b>Main Clock Frequency</b><br>Gives the number of main clock cycles within 16 slow clock periods.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="CKGR_MAINRDY"></a><b>CKGR_MAINRDY</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_MAINRDY">AT91C_CKGR_MAINRDY</a></font></td><td><b>Main Clock Ready</b><br>0 = FMAIN value is not valid or the main oscillator is disabled.<br>1 = The main oscillator has been enabled previously and MAINF value is available.</td></tr>
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<a name="CKGR_PLLR"></a><h4><a href="#CKGR">CKGR</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> CKGR_PLLR <i>PLL Register</i></h4><ul><null><font size="-2"><li><b>CKGR</b> <i><a href="AT91SAM7SE512_h.html#AT91C_CKGR_PLLR">AT91C_CKGR_PLLR</a></i> 0xFFFFFC2C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="CKGR_DIV"></a><b>CKGR_DIV</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_DIV">AT91C_CKGR_DIV</a></font></td><td><b>Divider Selected</b><br>2-255 Divider output is the selected clock divided by DIV<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_DIV_0"></a><b>CKGR_DIV_0</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_DIV_0">AT91C_CKGR_DIV_0</a></font></td><td><br>Divider output is 0</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_DIV_BYPASS"></a><b>CKGR_DIV_BYPASS</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_DIV_BYPASS">AT91C_CKGR_DIV_BYPASS</a></font></td><td><br>Divider is bypassed</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">13..8</td><td align="CENTER"><a name="CKGR_PLLCOUNT"></a><b>CKGR_PLLCOUNT</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_PLLCOUNT">AT91C_CKGR_PLLCOUNT</a></font></td><td><b>PLL Counter</b><br>Specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR after PMC_PLL is written.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="CKGR_OUT"></a><b>CKGR_OUT</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_OUT">AT91C_CKGR_OUT</a></font></td><td><b>PLL Output Frequency Range</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_OUT_0"></a><b>CKGR_OUT_0</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_OUT_0">AT91C_CKGR_OUT_0</a></font></td><td><br>Please refer to the PLL datasheet</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_OUT_1"></a><b>CKGR_OUT_1</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_OUT_1">AT91C_CKGR_OUT_1</a></font></td><td><br>Please refer to the PLL datasheet</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="CKGR_OUT_2"></a><b>CKGR_OUT_2</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_OUT_2">AT91C_CKGR_OUT_2</a></font></td><td><br>Please refer to the PLL datasheet</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="CKGR_OUT_3"></a><b>CKGR_OUT_3</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_OUT_3">AT91C_CKGR_OUT_3</a></font></td><td><br>Please refer to the PLL datasheet</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">26..16</td><td align="CENTER"><a name="CKGR_MUL"></a><b>CKGR_MUL</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_MUL">AT91C_CKGR_MUL</a></font></td><td><b>PLL Multiplier</b><br>0 = The PLL is deactivated.<br>1 up to 2047 = The PLL output frequency is the PLL input frequency multiplied by MUL + 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">29..28</td><td align="CENTER"><a name="CKGR_USBDIV"></a><b>CKGR_USBDIV</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_USBDIV">AT91C_CKGR_USBDIV</a></font></td><td><b>Divider for USB Clocks</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_USBDIV_0"></a><b>CKGR_USBDIV_0</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_USBDIV_0">AT91C_CKGR_USBDIV_0</a></font></td><td><br>Divider output is PLL clock output</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_USBDIV_1"></a><b>CKGR_USBDIV_1</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_USBDIV_1">AT91C_CKGR_USBDIV_1</a></font></td><td><br>Divider output is PLL clock output divided by 2</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="CKGR_USBDIV_2"></a><b>CKGR_USBDIV_2</b><font size="-1"><br><a href="AT91SAM7SE512_h.html#AT91C_CKGR_USBDIV_2">AT91C_CKGR_USBDIV_2</a></font></td><td><br>Divider output is PLL clock output divided by 4</td></tr>
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