</null></table>
<a name="SPI_RDR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> SPI_RDR  <i>Receive Data Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7SE512_h.html#AT91C_SPI_RDR">AT91C_SPI_RDR</a></i> 0xFFFE0008</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">15..0</td><td align="CENTER"><a name="SPI_RD"></a><b>SPI_RD</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_RD">AT91C_SPI_RD</a></font></td><td><b>Receive Data</b><br>Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19..16</td><td align="CENTER"><a name="SPI_RPCS"></a><b>SPI_RPCS</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_RPCS">AT91C_SPI_RPCS</a></font></td><td><b>Peripheral Chip Select Status</b><br>In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.</td></tr>
</null></table>
<a name="SPI_TDR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> SPI_TDR  <i>Transmit Data Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7SE512_h.html#AT91C_SPI_TDR">AT91C_SPI_TDR</a></i> 0xFFFE000C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">15..0</td><td align="CENTER"><a name="SPI_TD"></a><b>SPI_TD</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_TD">AT91C_SPI_TD</a></font></td><td><b>Transmit Data</b><br>Data which is to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be writ-ten to the transmit data register in a right-justified format.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19..16</td><td align="CENTER"><a name="SPI_TPCS"></a><b>SPI_TPCS</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_TPCS">AT91C_SPI_TPCS</a></font></td><td><b>Peripheral Chip Select Status</b><br>This field is only used if Variable Peripheral Select is active (PS = 1) and if the SPI is in Master Mode.<br>	If PCSDEC = 0:<br>		PCS = xxx0 NPCS[3:0] = 1110<br>		PCS = xx01 NPCS[3:0] = 1101<br>		PCS = x011 NPCS[3:0] = 1011<br>		PCS = 0111 NPCS[3:0] = 0111<br>		PCS = 1111 forbidden (no peripheral is selected)<br>		(x = don&#146;t care)<br>	If PCSDEC = 1:<br>		NPCS[3:0] output signals = PCS</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">24</td><td align="CENTER"><a name="SPI_LASTXFER"></a><b>SPI_LASTXFER</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_LASTXFER">AT91C_SPI_LASTXFER</a></font></td><td><b>SPI Last Transfer</b><br>0 = No effect.<br>1 = Deassert the NPCS after all transfers occured. Useful when CSAAT is set.</td></tr>
</null></table>
<a name="SPI_SR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> SPI_SR  <i>Status Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7SE512_h.html#AT91C_SPI_SR">AT91C_SPI_SR</a></i> 0xFFFE0010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SPI_RDRF"></a><b>SPI_RDRF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_RDRF">AT91C_SPI_RDRF</a></font></td><td><b>Receive Data Register Full</b><br>0 = No data has been received since the last read of SPI_RDR<br>1= Data has been received and the received data has been transferred from the serializer to SPI_RDR since the lastread of SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SPI_TDRE"></a><b>SPI_TDRE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_TDRE">AT91C_SPI_TDRE</a></font></td><td><b>Transmit Data Register Empty</b><br>0 = Data has been written to SPI_TDR and not yet transferred to the serializer.<br>1 = The last data written in the Transmit Data Register has been transferred in the serializer.<br>TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SPI_MODF"></a><b>SPI_MODF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_MODF">AT91C_SPI_MODF</a></font></td><td><b>Mode Fault Error</b><br>0 = No Mode Fault has been detected since the last read of SPI_SR.<br>1 = A Mode Fault occurred since the last read of the SPI_SR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SPI_OVRES"></a><b>SPI_OVRES</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_OVRES">AT91C_SPI_OVRES</a></font></td><td><b>Overrun Error Status</b><br>0 = No overrun has been detected since the last read of SPI_SR.<br>1 = An overrun has occurred since the last read of SPI_SR.<br>An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SPI_ENDRX"></a><b>SPI_ENDRX</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_ENDRX">AT91C_SPI_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SPI_ENDTX"></a><b>SPI_ENDTX</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_ENDTX">AT91C_SPI_ENDTX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SPI_RXBUFF"></a><b>SPI_RXBUFF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_RXBUFF">AT91C_SPI_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SPI_TXBUFE"></a><b>SPI_TXBUFE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_TXBUFE">AT91C_SPI_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="SPI_NSSR"></a><b>SPI_NSSR</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_NSSR">AT91C_SPI_NSSR</a></font></td><td><b>NSSR Interrupt</b><br>0 = No rising edge detected on NSS pin since last read.<br>1 = A rising edge occured on NSS pin since last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="SPI_TXEMPTY"></a><b>SPI_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_TXEMPTY">AT91C_SPI_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>As soon as a data is written in the SPI_TDR.<br>The SPI_TDR register and internal shifter are empty.<br>If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="SPI_SPIENS"></a><b>SPI_SPIENS</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_SPIENS">AT91C_SPI_SPIENS</a></font></td><td><b>Enable Status</b><br>0 = SPI is disabled.<br>1 = SPI is enabled.</td></tr>
</null></table>
<a name="SPI_IER"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> SPI_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7SE512_h.html#AT91C_SPI_IER">AT91C_SPI_IER</a></i> 0xFFFE0014</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SPI_RDRF"></a><b>SPI_RDRF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_RDRF">AT91C_SPI_RDRF</a></font></td><td><b>Receive Data Register Full</b><br>0 = No data has been received since the last read of SPI_RDR<br>1= Data has been received and the received data has been transferred from the serializer to SPI_RDR since the lastread of SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SPI_TDRE"></a><b>SPI_TDRE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_TDRE">AT91C_SPI_TDRE</a></font></td><td><b>Transmit Data Register Empty</b><br>0 = Data has been written to SPI_TDR and not yet transferred to the serializer.<br>1 = The last data written in the Transmit Data Register has been transferred in the serializer.<br>TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SPI_MODF"></a><b>SPI_MODF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_MODF">AT91C_SPI_MODF</a></font></td><td><b>Mode Fault Error</b><br>0 = No Mode Fault has been detected since the last read of SPI_SR.<br>1 = A Mode Fault occurred since the last read of the SPI_SR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SPI_OVRES"></a><b>SPI_OVRES</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_OVRES">AT91C_SPI_OVRES</a></font></td><td><b>Overrun Error Status</b><br>0 = No overrun has been detected since the last read of SPI_SR.<br>1 = An overrun has occurred since the last read of SPI_SR.<br>An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SPI_ENDRX"></a><b>SPI_ENDRX</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_ENDRX">AT91C_SPI_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SPI_ENDTX"></a><b>SPI_ENDTX</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_ENDTX">AT91C_SPI_ENDTX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SPI_RXBUFF"></a><b>SPI_RXBUFF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_RXBUFF">AT91C_SPI_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SPI_TXBUFE"></a><b>SPI_TXBUFE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_TXBUFE">AT91C_SPI_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="SPI_NSSR"></a><b>SPI_NSSR</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_NSSR">AT91C_SPI_NSSR</a></font></td><td><b>NSSR Interrupt</b><br>0 = No rising edge detected on NSS pin since last read.<br>1 = A rising edge occured on NSS pin since last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="SPI_TXEMPTY"></a><b>SPI_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_TXEMPTY">AT91C_SPI_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>As soon as a data is written in the SPI_TDR.<br>The SPI_TDR register and internal shifter are empty.<br>If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.</td></tr>
</null></table>
<a name="SPI_IDR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> SPI_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7SE512_h.html#AT91C_SPI_IDR">AT91C_SPI_IDR</a></i> 0xFFFE0018</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SPI_RDRF"></a><b>SPI_RDRF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_RDRF">AT91C_SPI_RDRF</a></font></td><td><b>Receive Data Register Full</b><br>0 = No data has been received since the last read of SPI_RDR<br>1= Data has been received and the received data has been transferred from the serializer to SPI_RDR since the lastread of SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SPI_TDRE"></a><b>SPI_TDRE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_TDRE">AT91C_SPI_TDRE</a></font></td><td><b>Transmit Data Register Empty</b><br>0 = Data has been written to SPI_TDR and not yet transferred to the serializer.<br>1 = The last data written in the Transmit Data Register has been transferred in the serializer.<br>TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SPI_MODF"></a><b>SPI_MODF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_MODF">AT91C_SPI_MODF</a></font></td><td><b>Mode Fault Error</b><br>0 = No Mode Fault has been detected since the last read of SPI_SR.<br>1 = A Mode Fault occurred since the last read of the SPI_SR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SPI_OVRES"></a><b>SPI_OVRES</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_OVRES">AT91C_SPI_OVRES</a></font></td><td><b>Overrun Error Status</b><br>0 = No overrun has been detected since the last read of SPI_SR.<br>1 = An overrun has occurred since the last read of SPI_SR.<br>An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SPI_ENDRX"></a><b>SPI_ENDRX</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_ENDRX">AT91C_SPI_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SPI_ENDTX"></a><b>SPI_ENDTX</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_ENDTX">AT91C_SPI_ENDTX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SPI_RXBUFF"></a><b>SPI_RXBUFF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_SPI_RXBUFF">AT91C_SPI_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>