-/*  * ISA space is 'always mapped' on currently supported MIPS systems, no need  * to explicitly ioremap() it. The fact that the ISA IO space is mapped  * to PAGE_OFFSET is pure coincidence - it does not mean ISA valuesdiff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/irq.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/irq.h--- linux-2.6.12-rc4/include/asm-mips/irq.h	2005-04-27 13:21:56.000000000 -0500+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/irq.h	2005-03-02 20:14:42.261778967 -0600@@ -24,11 +24,9 @@  struct pt_regs; -#ifdef CONFIG_PREEMPT- extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs); -#else+#ifdef CONFIG_PREEMPT  /*  * do_IRQ handles all normal device IRQ's (the specialdiff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/jmr3927/jmr3927.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/jmr3927/jmr3927.h--- linux-2.6.12-rc4/include/asm-mips/jmr3927/jmr3927.h	2004-10-18 16:54:29.000000000 -0500+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/jmr3927/jmr3927.h	2005-03-13 21:31:32.437868149 -0600@@ -202,20 +202,6 @@ #endif /* !__ASSEMBLY__ */  /*- * UART defines for serial.h- */--/* use Pre-scaler T0 (1/2) */-#define JMR3927_BASE_BAUD (JMR3927_IMCLK / 2 / 16)--#define UART0_ADDR   0xfffef300-#define UART1_ADDR   0xfffef400-#define UART0_INT    JMR3927_IRQ_IRC_SIO0-#define UART1_INT    JMR3927_IRQ_IRC_SIO1-#define UART0_FLAGS  ASYNC_BOOT_AUTOCONF-#define UART1_FLAGS  0--/*  * IRQ mappings  */ diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/mach-au1x00/au1000.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/mach-au1x00/au1000.h--- linux-2.6.12-rc4/include/asm-mips/mach-au1x00/au1000.h	2005-04-27 13:23:30.000000000 -0500+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/mach-au1x00/au1000.h	2005-04-22 20:34:46.906314208 -0500@@ -60,34 +60,34 @@ 	mdelay(ms); } -void static inline au_writeb(u8 val, int reg)+void static inline au_writeb(u8 val, unsigned long reg) { 	*(volatile u8 *)(reg) = val; } -void static inline au_writew(u16 val, int reg)+void static inline au_writew(u16 val, unsigned long reg) { 	*(volatile u16 *)(reg) = val; } -void static inline au_writel(u32 val, int reg)+void static inline au_writel(u32 val, unsigned long reg) { 	*(volatile u32 *)(reg) = val; } -static inline u8 au_readb(unsigned long port)+static inline u8 au_readb(unsigned long reg) {-	return (*(volatile u8 *)port);+	return (*(volatile u8 *)reg); } -static inline u16 au_readw(unsigned long port)+static inline u16 au_readw(unsigned long reg) {-	return (*(volatile u16 *)port);+	return (*(volatile u16 *)reg); } -static inline u32 au_readl(unsigned long port)+static inline u32 au_readl(unsigned long reg) {-	return (*(volatile u32 *)port);+	return (*(volatile u32 *)reg); }  /* These next three functions should be a generic part of the MIPS@@ -162,28 +162,293 @@ #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) #endif -/* SDRAM Controller */+/*+ * SDRAM Register Offsets+ */ #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)-#define MEM_SDMODE0                0xB4000000-#define MEM_SDMODE1                0xB4000004-#define MEM_SDMODE2                0xB4000008--#define MEM_SDADDR0                0xB400000C-#define MEM_SDADDR1                0xB4000010-#define MEM_SDADDR2                0xB4000014--#define MEM_SDREFCFG               0xB4000018-#define MEM_SDPRECMD               0xB400001C-#define MEM_SDAUTOREF              0xB4000020--#define MEM_SDWRMD0                0xB4000024-#define MEM_SDWRMD1                0xB4000028-#define MEM_SDWRMD2                0xB400002C+#define MEM_SDMODE0		(0x0000)+#define MEM_SDMODE1		(0x0004)+#define MEM_SDMODE2		(0x0008)+#define MEM_SDADDR0		(0x000C)+#define MEM_SDADDR1		(0x0010)+#define MEM_SDADDR2		(0x0014)+#define MEM_SDREFCFG	(0x0018)+#define MEM_SDPRECMD	(0x001C)+#define MEM_SDAUTOREF	(0x0020)+#define MEM_SDWRMD0		(0x0024)+#define MEM_SDWRMD1		(0x0028)+#define MEM_SDWRMD2		(0x002C)+#define MEM_SDSLEEP		(0x0030)+#define MEM_SDSMCKE		(0x0034)++/*+ * MEM_SDMODE register content definitions+ */+#define MEM_SDMODE_F		(1<<22)+#define MEM_SDMODE_SR		(1<<21)+#define MEM_SDMODE_BS		(1<<20)+#define MEM_SDMODE_RS		(3<<18)+#define MEM_SDMODE_CS		(7<<15)+#define MEM_SDMODE_TRAS		(15<<11)+#define MEM_SDMODE_TMRD		(3<<9)+#define MEM_SDMODE_TWR		(3<<7)+#define MEM_SDMODE_TRP		(3<<5)+#define MEM_SDMODE_TRCD		(3<<3)+#define MEM_SDMODE_TCL		(7<<0)++#define MEM_SDMODE_BS_2Bank	(0<<20)+#define MEM_SDMODE_BS_4Bank	(1<<20)+#define MEM_SDMODE_RS_11Row	(0<<18)+#define MEM_SDMODE_RS_12Row	(1<<18)+#define MEM_SDMODE_RS_13Row	(2<<18)+#define MEM_SDMODE_RS_N(N)	((N)<<18)+#define MEM_SDMODE_CS_7Col	(0<<15)+#define MEM_SDMODE_CS_8Col	(1<<15)+#define MEM_SDMODE_CS_9Col	(2<<15)+#define MEM_SDMODE_CS_10Col	(3<<15)+#define MEM_SDMODE_CS_11Col	(4<<15)+#define MEM_SDMODE_CS_N(N)		((N)<<15)+#define MEM_SDMODE_TRAS_N(N)	((N)<<11)+#define MEM_SDMODE_TMRD_N(N)	((N)<<9)+#define MEM_SDMODE_TWR_N(N)		((N)<<7)+#define MEM_SDMODE_TRP_N(N)		((N)<<5)+#define MEM_SDMODE_TRCD_N(N)	((N)<<3)+#define MEM_SDMODE_TCL_N(N)		((N)<<0)++/*+ * MEM_SDADDR register contents definitions+ */+#define MEM_SDADDR_E			(1<<20)+#define MEM_SDADDR_CSBA			(0x03FF<<10)+#define MEM_SDADDR_CSMASK		(0x03FF<<0)+#define MEM_SDADDR_CSBA_N(N)	((N)&(0x03FF<<22)>>12)+#define MEM_SDADDR_CSMASK_N(N)	((N)&(0x03FF<<22)>>22)++/*+ * MEM_SDREFCFG register content definitions+ */+#define MEM_SDREFCFG_TRC		(15<<28)+#define MEM_SDREFCFG_TRPM		(3<<26)+#define MEM_SDREFCFG_E			(1<<25)+#define MEM_SDREFCFG_RE			(0x1ffffff<<0)+#define MEM_SDREFCFG_TRC_N(N)	((N)<<MEM_SDREFCFG_TRC)+#define MEM_SDREFCFG_TRPM_N(N)	((N)<<MEM_SDREFCFG_TRPM)+#define MEM_SDREFCFG_REF_N(N)	(N)+#endif++/***********************************************************************/ -#define MEM_SDSLEEP                0xB4000030-#define MEM_SDSMCKE                0xB4000034+/*+ * Au1550 SDRAM Register Offsets+ */++/***********************************************************************/++#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)+#define MEM_SDMODE0		(0x0800)+#define MEM_SDMODE1		(0x0808)+#define MEM_SDMODE2		(0x0810)+#define MEM_SDADDR0		(0x0820)+#define MEM_SDADDR1		(0x0828)+#define MEM_SDADDR2		(0x0830)+#define MEM_SDCONFIGA	(0x0840)+#define MEM_SDCONFIGB	(0x0848)+#define MEM_SDSTAT		(0x0850)+#define MEM_SDERRADDR	(0x0858)+#define MEM_SDSTRIDE0	(0x0860)+#define MEM_SDSTRIDE1	(0x0868)+#define MEM_SDSTRIDE2	(0x0870)+#define MEM_SDWRMD0		(0x0880)+#define MEM_SDWRMD1		(0x0888)+#define MEM_SDWRMD2		(0x0890)+#define MEM_SDPRECMD	(0x08C0)+#define MEM_SDAUTOREF	(0x08C8)+#define MEM_SDSREF		(0x08D0)+#define MEM_SDSLEEP		MEM_SDSREF++#endif++/*+ * Physical base addresses for integrated peripherals+ */++#ifdef CONFIG_SOC_AU1000+#define	MEM_PHYS_ADDR		0x14000000+#define	STATIC_MEM_PHYS_ADDR	0x14001000+#define	DMA0_PHYS_ADDR		0x14002000+#define	DMA1_PHYS_ADDR		0x14002100+#define	DMA2_PHYS_ADDR		0x14002200+#define	DMA3_PHYS_ADDR		0x14002300+#define	DMA4_PHYS_ADDR		0x14002400+#define	DMA5_PHYS_ADDR		0x14002500+#define	DMA6_PHYS_ADDR		0x14002600+#define	DMA7_PHYS_ADDR		0x14002700+#define	IC0_PHYS_ADDR		0x10400000+#define	IC1_PHYS_ADDR		0x11800000+#define	AC97_PHYS_ADDR		0x10000000+#define	USBH_PHYS_ADDR		0x10100000+#define	USBD_PHYS_ADDR		0x10200000+#define	IRDA_PHYS_ADDR		0x10300000+#define	MAC0_PHYS_ADDR		0x10500000+#define	MAC1_PHYS_ADDR		0x10510000+#define	MACEN_PHYS_ADDR		0x10520000+#define	MACDMA0_PHYS_ADDR	0x14004000+#define	MACDMA1_PHYS_ADDR	0x14004200+#define	I2S_PHYS_ADDR		0x11000000+#define	UART0_PHYS_ADDR		0x11100000+#define	UART1_PHYS_ADDR		0x11200000+#define	UART2_PHYS_ADDR		0x11300000+#define	UART3_PHYS_ADDR		0x11400000+#define	SSI0_PHYS_ADDR		0x11600000+#define	SSI1_PHYS_ADDR		0x11680000+#define	SYS_PHYS_ADDR		0x11900000+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL #endif +/********************************************************************/++#ifdef CONFIG_SOC_AU1500+#define	MEM_PHYS_ADDR		0x14000000+#define	STATIC_MEM_PHYS_ADDR	0x14001000+#define	DMA0_PHYS_ADDR		0x14002000+#define	DMA1_PHYS_ADDR		0x14002100+#define	DMA2_PHYS_ADDR		0x14002200+#define	DMA3_PHYS_ADDR		0x14002300+#define	DMA4_PHYS_ADDR		0x14002400+#define	DMA5_PHYS_ADDR		0x14002500+#define	DMA6_PHYS_ADDR		0x14002600+#define	DMA7_PHYS_ADDR		0x14002700+#define	IC0_PHYS_ADDR		0x10400000+#define	IC1_PHYS_ADDR		0x11800000+#define	AC97_PHYS_ADDR		0x10000000+#define	USBH_PHYS_ADDR		0x10100000+#define	USBD_PHYS_ADDR		0x10200000+#define PCI_PHYS_ADDR		0x14005000+#define	MAC0_PHYS_ADDR		0x11500000+#define	MAC1_PHYS_ADDR		0x11510000+#define	MACEN_PHYS_ADDR		0x11520000+#define	MACDMA0_PHYS_ADDR	0x14004000+#define	MACDMA1_PHYS_ADDR	0x14004200+#define	I2S_PHYS_ADDR		0x11000000+#define	UART0_PHYS_ADDR		0x11100000+#define	UART3_PHYS_ADDR		0x11400000+#define GPIO2_PHYS_ADDR		0x11700000+#define	SYS_PHYS_ADDR		0x11900000+#define PCI_MEM_PHYS_ADDR     0x400000000ULL+#define PCI_IO_PHYS_ADDR      0x500000000ULL+#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL+#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL+#endif++/********************************************************************/++#ifdef CONFIG_SOC_AU1100+#define	MEM_PHYS_ADDR		0x14000000+#define	STATIC_MEM_PHYS_ADDR	0x14001000+#define	DMA0_PHYS_ADDR		0x14002000+#define	DMA1_PHYS_ADDR		0x14002100+#define	DMA2_PHYS_ADDR		0x14002200+#define	DMA3_PHYS_ADDR		0x14002300+#define	DMA4_PHYS_ADDR		0x14002400+#define	DMA5_PHYS_ADDR		0x14002500+#define	DMA6_PHYS_ADDR		0x14002600+#define	DMA7_PHYS_ADDR		0x14002700+#define	IC0_PHYS_ADDR		0x10400000+#define SD0_PHYS_ADDR		0x10600000+#define SD1_PHYS_ADDR		0x10680000+#define	IC1_PHYS_ADDR		0x11800000+#define	AC97_PHYS_ADDR		0x10000000+#define	USBH_PHYS_ADDR		0x10100000+#define	USBD_PHYS_ADDR		0x10200000+#define	IRDA_PHYS_ADDR		0x10300000+#define	MAC0_PHYS_ADDR		0x10500000+#define	MACEN_PHYS_ADDR		0x10520000+#define	MACDMA0_PHYS_ADDR	0x14004000+#define	MACDMA1_PHYS_ADDR	0x14004200+#define	I2S_PHYS_ADDR		0x11000000+#define	UART0_PHYS_ADDR		0x11100000+#define	UART1_PHYS_ADDR		0x11200000+#define	UART3_PHYS_ADDR		0x11400000+#define	SSI0_PHYS_ADDR		0x11600000+#define	SSI1_PHYS_ADDR		0x11680000+#define GPIO2_PHYS_ADDR		0x11700000+#define	SYS_PHYS_ADDR		0x11900000+#define LCD_PHYS_ADDR		0x15000000+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL+#endif++/***********************************************************************/++#ifdef CONFIG_SOC_AU1550+#define	MEM_PHYS_ADDR		0x14000000+#define	STATIC_MEM_PHYS_ADDR	0x14001000+#define	IC0_PHYS_ADDR		0x10400000+#define	IC1_PHYS_ADDR		0x11800000+#define	USBH_PHYS_ADDR		0x14020000+#define	USBD_PHYS_ADDR		0x10200000+#define PCI_PHYS_ADDR		0x14005000+#define	MAC0_PHYS_ADDR		0x10500000+#define	MAC1_PHYS_ADDR		0x10510000+#define	MACEN_PHYS_ADDR		0x10520000+#define	MACDMA0_PHYS_ADDR	0x14004000+#define	MACDMA1_PHYS_ADDR	0x14004200+#define	UART0_PHYS_ADDR		0x11100000+#define	UART1_PHYS_ADDR		0x11200000+#define	UART3_PHYS_ADDR		0x11400000+#define GPIO2_PHYS_ADDR		0x11700000+#define	SYS_PHYS_ADDR		0x11900000+#define	DDMA_PHYS_ADDR		0x14002000+#define PE_PHYS_ADDR		0x14008000+#define PSC0_PHYS_ADDR	 	0x11A00000+#define PSC1_PHYS_ADDR	 	0x11B00000+#define PSC2_PHYS_ADDR	 	0x10A00000+#define PSC3_PHYS_ADDR	 	0x10B00000+#define PCI_MEM_PHYS_ADDR     0x400000000ULL+#define PCI_IO_PHYS_ADDR      0x500000000ULL+#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL+#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL+#endif++/***********************************************************************/++#ifdef CONFIG_SOC_AU1200+#define	MEM_PHYS_ADDR		0x14000000+#define	STATIC_MEM_PHYS_ADDR	0x14001000+#define AES_PHYS_ADDR		0x10300000+#define CIM_PHYS_ADDR		0x14004000+#define	IC0_PHYS_ADDR		0x10400000+#define	IC1_PHYS_ADDR		0x11800000+#define USBM_PHYS_ADDR		0x14020000+#define	USBH_PHYS_ADDR		0x14020100+#define	UART0_PHYS_ADDR		0x11100000+#define	UART1_PHYS_ADDR		0x11200000+#define GPIO2_PHYS_ADDR		0x11700000+#define	SYS_PHYS_ADDR		0x11900000+#define	DDMA_PHYS_ADDR		0x14002000+#define PSC0_PHYS_ADDR	 	0x11A00000+#define PSC1_PHYS_ADDR	 	0x11B00000+#define SD0_PHYS_ADDR		0x10600000+#define SD1_PHYS_ADDR		0x10680000+#define LCD_PHYS_ADDR		0x15000000+#define SWCNT_PHYS_ADDR		0x1110010C