+#define MAEFE_PHYS_ADDR		0x14012000+#define MAEBE_PHYS_ADDR		0x14010000+#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL+#endif++ /* Static Bus Controller */ #define MEM_STCFG0                 0xB4001000 #define MEM_STTIME0                0xB4001004@@ -369,7 +634,7 @@ #define AU1000_MAC0_ENABLE       0xB0520000 #define AU1000_MAC1_ENABLE       0xB0520004 #define NUM_ETH_INTERFACES 2-#endif // CONFIG_SOC_AU1000+#endif /* CONFIG_SOC_AU1000 */  /* Au1500 */ #ifdef CONFIG_SOC_AU1500@@ -429,6 +694,12 @@ #define AU1500_GPIO_207           62 #define AU1500_GPIO_208_215       63 +/* shortcuts */+#define INTA AU1000_PCI_INTA+#define INTB AU1000_PCI_INTB+#define INTC AU1000_PCI_INTC+#define INTD AU1000_PCI_INTD+ #define UART0_ADDR                0xB1100000 #define UART3_ADDR                0xB1400000 @@ -440,7 +711,7 @@ #define AU1500_MAC0_ENABLE       0xB1520000 #define AU1500_MAC1_ENABLE       0xB1520004 #define NUM_ETH_INTERFACES 2-#endif // CONFIG_SOC_AU1500+#endif /* CONFIG_SOC_AU1500 */  /* Au1100 */ #ifdef CONFIG_SOC_AU1100@@ -485,6 +756,22 @@ #define AU1000_GPIO_13            45 #define AU1000_GPIO_14            46 #define AU1000_GPIO_15            47+#define AU1000_GPIO_16            48+#define AU1000_GPIO_17            49+#define AU1000_GPIO_18            50+#define AU1000_GPIO_19            51+#define AU1000_GPIO_20            52+#define AU1000_GPIO_21            53+#define AU1000_GPIO_22            54+#define AU1000_GPIO_23            55+#define AU1000_GPIO_24            56+#define AU1000_GPIO_25            57+#define AU1000_GPIO_26            58+#define AU1000_GPIO_27            59+#define AU1000_GPIO_28            60+#define AU1000_GPIO_29            61+#define AU1000_GPIO_30            62+#define AU1000_GPIO_31            63  #define UART0_ADDR                0xB1100000 #define UART1_ADDR                0xB1200000@@ -496,7 +783,7 @@ #define AU1100_ETH0_BASE	  0xB0500000 #define AU1100_MAC0_ENABLE       0xB0520000 #define NUM_ETH_INTERFACES 1-#endif // CONFIG_SOC_AU1100+#endif /* CONFIG_SOC_AU1100 */  #ifdef CONFIG_SOC_AU1550 #define AU1550_UART0_INT          0@@ -513,14 +800,14 @@ #define AU1550_PSC1_INT           11 #define AU1550_PSC2_INT           12 #define AU1550_PSC3_INT           13-#define AU1550_TOY_INT			  14-#define AU1550_TOY_MATCH0_INT     15-#define AU1550_TOY_MATCH1_INT     16-#define AU1550_TOY_MATCH2_INT     17-#define AU1550_RTC_INT            18-#define AU1550_RTC_MATCH0_INT     19-#define AU1550_RTC_MATCH1_INT     20-#define AU1550_RTC_MATCH2_INT     21+#define AU1000_TOY_INT			  14+#define AU1000_TOY_MATCH0_INT     15+#define AU1000_TOY_MATCH1_INT     16+#define AU1000_TOY_MATCH2_INT     17+#define AU1000_RTC_INT            18+#define AU1000_RTC_MATCH0_INT     19+#define AU1000_RTC_MATCH1_INT     20+#define AU1000_RTC_MATCH2_INT     21 #define AU1550_NAND_INT           23 #define AU1550_USB_DEV_REQ_INT    24 #define AU1550_USB_DEV_SUS_INT    25@@ -563,6 +850,12 @@ #define AU1500_GPIO_207           62 #define AU1500_GPIO_208_218       63	// Logical or of GPIO208:218 +/* shortcuts */+#define INTA AU1550_PCI_INTA+#define INTB AU1550_PCI_INTB+#define INTC AU1550_PCI_INTC+#define INTD AU1550_PCI_INTD+ #define UART0_ADDR                0xB1100000 #define UART1_ADDR                0xB1200000 #define UART3_ADDR                0xB1400000@@ -575,7 +868,7 @@ #define AU1550_MAC0_ENABLE       0xB0520000 #define AU1550_MAC1_ENABLE       0xB0520004 #define NUM_ETH_INTERFACES 2-#endif // CONFIG_SOC_AU1550+#endif /* CONFIG_SOC_AU1550 */  #ifdef CONFIG_SOC_AU1200 #define AU1200_UART0_INT          0@@ -592,14 +885,14 @@ #define AU1200_PSC1_INT           11 #define AU1200_AES_INT            12 #define AU1200_CAMERA_INT         13-#define AU1200_TOY_INT			  14-#define AU1200_TOY_MATCH0_INT     15-#define AU1200_TOY_MATCH1_INT     16-#define AU1200_TOY_MATCH2_INT     17-#define AU1200_RTC_INT            18-#define AU1200_RTC_MATCH0_INT     19-#define AU1200_RTC_MATCH1_INT     20-#define AU1200_RTC_MATCH2_INT     21+#define AU1000_TOY_INT			  14+#define AU1000_TOY_MATCH0_INT     15+#define AU1000_TOY_MATCH1_INT     16+#define AU1000_TOY_MATCH2_INT     17+#define AU1000_RTC_INT            18+#define AU1000_RTC_MATCH0_INT     19+#define AU1000_RTC_MATCH1_INT     20+#define AU1000_RTC_MATCH2_INT     21 #define AU1200_NAND_INT           23 #define AU1200_GPIO_204           24 #define AU1200_GPIO_205           25@@ -607,6 +900,7 @@ #define AU1200_GPIO_207           27 #define AU1200_GPIO_208_215       28 // Logical OR of 208:215 #define AU1200_USB_INT            29+#define AU1000_USB_HOST_INT		  AU1200_USB_INT #define AU1200_LCD_INT            30 #define AU1200_MAE_BOTH_INT       31 #define AU1000_GPIO_0             32@@ -645,20 +939,36 @@ #define UART0_ADDR                0xB1100000 #define UART1_ADDR                0xB1200000 -#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap-#define USB_HOST_CONFIG           0xB4027ffc+#define USB_UOC_BASE              0x14020020+#define USB_UOC_LEN               0x20+#define USB_OHCI_BASE             0x14020100+#define USB_OHCI_LEN              0x100+#define USB_EHCI_BASE             0x14020200+#define USB_EHCI_LEN              0x100+#define USB_UDC_BASE              0x14022000+#define USB_UDC_LEN               0x2000+#define USB_MSR_BASE			  0xB4020000+#define USB_MSR_MCFG              4+#define USBMSRMCFG_OMEMEN         0+#define USBMSRMCFG_OBMEN          1+#define USBMSRMCFG_EMEMEN         2+#define USBMSRMCFG_EBMEN          3+#define USBMSRMCFG_DMEMEN         4+#define USBMSRMCFG_DBMEN          5+#define USBMSRMCFG_GMEMEN         6+#define USBMSRMCFG_OHCCLKEN       16+#define USBMSRMCFG_EHCCLKEN       17+#define USBMSRMCFG_UDCCLKEN       18+#define USBMSRMCFG_PHYPLLEN       19+#define USBMSRMCFG_RDCOMB         30+#define USBMSRMCFG_PFEN           31 -// these are here for prototyping on au1550 (do not exist on au1200)-#define AU1200_ETH0_BASE      0xB0500000-#define AU1200_ETH1_BASE      0xB0510000-#define AU1200_MAC0_ENABLE       0xB0520000-#define AU1200_MAC1_ENABLE       0xB0520004-#define NUM_ETH_INTERFACES 2-#endif // CONFIG_SOC_AU1200+#endif /* CONFIG_SOC_AU1200 */  #define AU1000_LAST_INTC0_INT     31+#define AU1000_LAST_INTC1_INT     63 #define AU1000_MAX_INTR           63-+#define INTX    		0xFF /* not valid */  /* Programmable Counters 0 and 1 */ #define SYS_BASE                   0xB1900000@@ -730,6 +1040,8 @@   #define I2S_CONTROL_D         (1<<1)   #define I2S_CONTROL_CE        (1<<0) +#ifndef CONFIG_SOC_AU1200+ /* USB Host Controller */ #define USB_OHCI_LEN              0x00100000 @@ -775,6 +1087,8 @@   #define USBDEV_ENABLE (1<<1)   #define USBDEV_CE     (1<<0) +#endif /* !CONFIG_SOC_AU1200 */+ /* Ethernet Controllers  */  /* 4 byte offsets from AU1000_ETH_BASE */@@ -1173,6 +1487,37 @@   #define SYS_PF_PSC1_S1		(1 << 1)   #define SYS_PF_MUST_BE_SET		((1 << 5) | (1 << 2)) +/* Au1200 Only */+#ifdef CONFIG_SOC_AU1200+#define SYS_PINFUNC_DMA		(1<<31)+#define SYS_PINFUNC_S0A		(1<<30)+#define SYS_PINFUNC_S1A		(1<<29)+#define SYS_PINFUNC_LP0		(1<<28)+#define SYS_PINFUNC_LP1		(1<<27)+#define SYS_PINFUNC_LD16	(1<<26)+#define SYS_PINFUNC_LD8		(1<<25)+#define SYS_PINFUNC_LD1		(1<<24)+#define SYS_PINFUNC_LD0		(1<<23)+#define SYS_PINFUNC_P1A		(3<<21)+#define SYS_PINFUNC_P1B		(1<<20)+#define SYS_PINFUNC_FS3		(1<<19)+#define SYS_PINFUNC_P0A		(3<<17)+#define SYS_PINFUNC_CS		(1<<16)+#define SYS_PINFUNC_CIM		(1<<15)+#define SYS_PINFUNC_P1C		(1<<14)+#define SYS_PINFUNC_U1T		(1<<12)+#define SYS_PINFUNC_U1R		(1<<11)+#define SYS_PINFUNC_EX1		(1<<10)+#define SYS_PINFUNC_EX0		(1<<9)+#define SYS_PINFUNC_U0R		(1<<8)+#define SYS_PINFUNC_MC		(1<<7)+#define SYS_PINFUNC_S0B		(1<<6)+#define SYS_PINFUNC_S0C		(1<<5)+#define SYS_PINFUNC_P0B		(1<<4)+#define SYS_PINFUNC_U0T		(1<<3)+#define SYS_PINFUNC_S1B		(1<<2)+#endif+ #define SYS_TRIOUTRD              0xB1900100 #define SYS_TRIOUTCLR             0xB1900100 #define SYS_OUTPUTRD              0xB1900108@@ -1239,6 +1584,12 @@   #define SYS_CS_MI2_MASK           (0x7<<SYS_CS_MI2_BIT)   #define SYS_CS_DI2                (1<<16)   #define SYS_CS_CI2                (1<<15)+#ifdef CONFIG_SOC_AU1100+  #define SYS_CS_ML_BIT             7+  #define SYS_CS_ML_MASK            (0x7<<SYS_CS_ML_BIT)+  #define SYS_CS_DL                 (1<<6)+  #define SYS_CS_CL                 (1<<5)+#else   #define SYS_CS_MUH_BIT            12   #define SYS_CS_MUH_MASK           (0x7<<SYS_CS_MUH_BIT)   #define SYS_CS_DUH                (1<<11)@@ -1247,6 +1598,7 @@   #define SYS_CS_MUD_MASK           (0x7<<SYS_CS_MUD_BIT)   #define SYS_CS_DUD                (1<<6)   #define SYS_CS_CUD                (1<<5)+#endif   #define SYS_CS_MIR_BIT            2   #define SYS_CS_MIR_MASK           (0x7<<SYS_CS_MIR_BIT)   #define SYS_CS_DIR                (1<<1)@@ -1300,7 +1652,6 @@ #define SD1_XMIT_FIFO	0xB0680000 #define SD1_RECV_FIFO	0xB0680004 - #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) /* Au1500 PCI Controller */ #define Au1500_CFG_BASE           0xB4005000 // virtual, kseg0 addr@@ -1363,36 +1714,77 @@ 		      _ctl_; })  -#else /* Au1000 and Au1100 */+#else /* Au1000 and Au1100 and Au1200 */  /* don't allow any legacy ports probing */-#define IOPORT_RESOURCE_START 0x10000000;+#define IOPORT_RESOURCE_START 0x10000000 #define IOPORT_RESOURCE_END   0xffffffff #define IOMEM_RESOURCE_START  0x10000000 #define IOMEM_RESOURCE_END    0xffffffff -#ifdef CONFIG_MIPS_PB1000-#define PCI_IO_START      0x10000000-#define PCI_IO_END        0x1000ffff-#define PCI_MEM_START     0x18000000-#define PCI_MEM_END       0x18ffffff-#define PCI_FIRST_DEVFN   0-#define PCI_LAST_DEVFN    1-#else-/* no PCI bus controller */ #define PCI_IO_START    0 #define PCI_IO_END      0 #define PCI_MEM_START   0-#define PCI_MEM_END     0 +#define PCI_MEM_END     0 #define PCI_FIRST_DEVFN 0 #define PCI_LAST_DEVFN  0-#endif  #endif +#ifndef _LANGUAGE_ASSEMBLY+typedef volatile struct+{+	/* 0x0000 */ u32 toytrim;+	/* 0x0004 */ u32 toywrite;+	/* 0x0008 */ u32 toymatch0;+	/* 0x000C */ u32 toymatch1;+	/* 0x0010 */ u32 toymatch2;+	/* 0x0014 */ u32 cntrctrl;+	/* 0x0018 */ u32 scratch0;+	/* 0x001C */ u32 scratch1;+	/* 0x0020 */ u32 freqctrl0;+	/* 0x0024 */ u32 freqctrl1;+	/* 0x0028 */ u32 clksrc;+	/* 0x002C */ u32 pinfunc;+	/* 0x0030 */ u32 reserved0;+	/* 0x0034 */ u32 wakemsk;+	/* 0x0038 */ u32 endian;+	/* 0x003C */ u32 powerctrl;+	/* 0x0040 */ u32 toyread;+	/* 0x0044 */ u32 rtctrim;+	/* 0x0048 */ u32 rtcwrite;+	/* 0x004C */ u32 rtcmatch0;+	/* 0x0050 */ u32 rtcmatch1;+	/* 0x0054 */ u32 rtcmatch2;+	/* 0x0058 */ u32 rtcread;+	/* 0x005C */ u32 wakesrc;+	/* 0x0060 */ u32 cpupll;+	/* 0x0064 */ u32 auxpll;+	/* 0x0068 */ u32 reserved1;+	/* 0x006C */ u32 reserved2;+	/* 0x0070 */ u32 reserved3;+	/* 0x0074 */ u32 reserved4;+	/* 0x0078 */ u32 slppwr;+	/* 0x007C */ u32 sleep;+	/* 0x0080 */ u32 reserved5[32];+	/* 0x0100 */ u32 trioutrd;+#define trioutclr trioutrd+	/* 0x0104 */ u32 reserved6;+	/* 0x0108 */ u32 outputrd;+#define outputset outputrd+	/* 0x010C */ u32 outputclr;+	/* 0x0110 */ u32 pinstaterd;+#define pininputen pinstaterd++} AU1X00_SYS;++static AU1X00_SYS* const sys  = (AU1X00_SYS *)SYS_BASE;++#endif /* Processor information base on prid.  * Copied from PowerPC.  */+#ifndef _LANGUAGE_ASSEMBLY struct cpu_spec { 	/* CPU is matched via (PRID & prid_mask) == prid_value */ 	unsigned int	prid_mask;@@ -1406,3 +1798,6 @@ extern struct cpu_spec		cpu_specs[]; extern struct cpu_spec		*cur_cpu_spec[]; #endif++#endif+diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/mach-au1x00/au1xxx_dbdma.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/mach-au1x00/au1xxx_dbdma.h--- linux-2.6.12-rc4/include/asm-mips/mach-au1x00/au1xxx_dbdma.h	2005-04-27 13:23:30.000000000 -0500+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/mach-au1x00/au1xxx_dbdma.h	2005-03-02 20:14:42.483744322 -0600@@ -45,7 +45,7 @@ #define DDMA_GLOBAL_BASE	0xb4003000 #define DDMA_CHANNEL_BASE	0xb4002000 -typedef struct dbdma_global {+typedef volatile struct dbdma_global { 	u32	ddma_config; 	u32	ddma_intstat; 	u32	ddma_throttle;