@@ -62,7 +62,7 @@  /* The structure of a DMA Channel. */-typedef struct au1xxx_dma_channel {+typedef volatile struct au1xxx_dma_channel { 	u32	ddma_cfg;	/* See below */ 	u32	ddma_desptr;	/* 32-byte aligned pointer to descriptor */ 	u32	ddma_statptr;	/* word aligned pointer to status word */@@ -98,7 +98,7 @@ /* "Standard" DDMA Descriptor.  * Must be 32-byte aligned.  */-typedef struct au1xxx_ddma_desc {+typedef volatile struct au1xxx_ddma_desc { 	u32	dscr_cmd0;		/* See below */ 	u32	dscr_cmd1;		/* See below */ 	u32	dscr_source0;		/* source phys address */@@ -107,6 +107,12 @@ 	u32	dscr_dest1;		/* See below */ 	u32	dscr_stat;		/* completion status */ 	u32	dscr_nxtptr;		/* Next descriptor pointer (mostly) */+	/* First 32bytes are HW specific!!!+	   Lets have some SW data following.. make sure its 32bytes+	 */+	u32	sw_status;+	u32 	sw_context;+	u32	sw_reserved[6]; } au1x_ddma_desc_t;  #define DSCR_CMD0_V		(1 << 31)	/* Descriptor valid */@@ -125,8 +131,11 @@ #define DSCR_CMD0_CV		(0x1 << 2)	/* Clear Valid when done */ #define DSCR_CMD0_ST_MASK	(0x3 << 0)	/* Status instruction */ +#define SW_STATUS_INUSE		(1<<0)+ /* Command 0 device IDs. */+#ifdef CONFIG_SOC_AU1550 #define DSCR_CMD0_UART0_TX	0 #define DSCR_CMD0_UART0_RX	1 #define DSCR_CMD0_UART3_TX	2@@ -155,9 +164,45 @@ #define DSCR_CMD0_MAC0_TX	25 #define DSCR_CMD0_MAC1_RX	26 #define DSCR_CMD0_MAC1_TX	27+#endif /* CONFIG_SOC_AU1550 */++#ifdef CONFIG_SOC_AU1200+#define DSCR_CMD0_UART0_TX	0+#define DSCR_CMD0_UART0_RX	1+#define DSCR_CMD0_UART1_TX	2+#define DSCR_CMD0_UART1_RX	3+#define DSCR_CMD0_DMA_REQ0	4+#define DSCR_CMD0_DMA_REQ1	5+#define DSCR_CMD0_MAE_BE	6+#define DSCR_CMD0_MAE_FE	7+#define DSCR_CMD0_SDMS_TX0	8+#define DSCR_CMD0_SDMS_RX0	9+#define DSCR_CMD0_SDMS_TX1	10+#define DSCR_CMD0_SDMS_RX1	11+#define DSCR_CMD0_AES_TX	13+#define DSCR_CMD0_AES_RX	12+#define DSCR_CMD0_PSC0_TX	14+#define DSCR_CMD0_PSC0_RX	15+#define DSCR_CMD0_PSC1_TX	16+#define DSCR_CMD0_PSC1_RX	17+#define DSCR_CMD0_CIM_RXA	18+#define DSCR_CMD0_CIM_RXB	19+#define DSCR_CMD0_CIM_RXC	20+#define DSCR_CMD0_MAE_BOTH	21+#define DSCR_CMD0_LCD		22+#define DSCR_CMD0_NAND_FLASH	23+#define DSCR_CMD0_PSC0_SYNC	24+#define DSCR_CMD0_PSC1_SYNC	25+#define DSCR_CMD0_CIM_SYNC	26+#endif /* CONFIG_SOC_AU1200 */+ #define DSCR_CMD0_THROTTLE	30 #define DSCR_CMD0_ALWAYS	31 #define DSCR_NDEV_IDS		32+/* THis macro is used to find/create custom device types */+#define DSCR_DEV2CUSTOM_ID(x,d)	(((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))+#define DSCR_CUSTOM2DEV_ID(x)	((x)&0xFF)+  #define DSCR_CMD0_SID(x)	(((x) & 0x1f) << 25) #define DSCR_CMD0_DID(x)	(((x) & 0x1f) << 20)@@ -246,6 +291,43 @@ */ #define NUM_DBDMA_CHANS	16 +/*+ * Ddma API definitions+ * FIXME: may not fit to this header file+ */+typedef struct dbdma_device_table {+	u32		dev_id;+	u32		dev_flags;+	u32		dev_tsize;+	u32		dev_devwidth;+	u32		dev_physaddr;		/* If FIFO */+	u32		dev_intlevel;+	u32		dev_intpolarity;+} dbdev_tab_t;+++typedef struct dbdma_chan_config {+	spinlock_t      lock;++	u32			chan_flags;+	u32			chan_index;+	dbdev_tab_t		*chan_src;+	dbdev_tab_t		*chan_dest;+	au1x_dma_chan_t		*chan_ptr;+	au1x_ddma_desc_t	*chan_desc_base;+	au1x_ddma_desc_t	*get_ptr, *put_ptr, *cur_ptr;+	void			*chan_callparam;+	void (*chan_callback)(int, void *, struct pt_regs *);+} chan_tab_t;++#define DEV_FLAGS_INUSE		(1 << 0)+#define DEV_FLAGS_ANYUSE	(1 << 1)+#define DEV_FLAGS_OUT		(1 << 2)+#define DEV_FLAGS_IN		(1 << 3)+#define DEV_FLAGS_BURSTABLE (1 << 4)+#define DEV_FLAGS_SYNC		(1 << 5)+/* end Ddma API definitions */+ /* External functions for drivers to use. */ /* Use this to allocate a dbdma channel.  The device ids are one of the@@ -258,18 +340,6 @@  #define DBDMA_MEM_CHAN	DSCR_CMD0_ALWAYS -/* ACK!  These should be in a board specific description file.-*/-#ifdef CONFIG_MIPS_PB1550-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX-#endif-#ifdef CONFIG_MIPS_DB1550-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX-#endif-- /* Set the device width of a in/out fifo. */ u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);@@ -280,8 +350,8 @@  /* Put buffers on source/destination descriptors. */-u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes);-u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes);+u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);+u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);  /* Get a buffer from the destination descriptor. */@@ -295,5 +365,25 @@ void au1xxx_dbdma_chan_free(u32 chanid); void au1xxx_dbdma_dump(u32 chanid); +u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );++u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );++/*+ 	Some compatibilty macros --+		Needed to make changes to API without breaking existing drivers+*/+#define	au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)+#define	au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)++#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)+#define	au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)++/*+ *	Flags for the put_source/put_dest functions.+ */+#define DDMA_FLAGS_IE	(1<<0)+#define DDMA_FLAGS_NOIE (1<<1)+ #endif /* _LANGUAGE_ASSEMBLY */ #endif /* _AU1000_DBDMA_H_ */diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/mach-au1x00/au1xxx_psc.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/mach-au1x00/au1xxx_psc.h--- linux-2.6.12-rc4/include/asm-mips/mach-au1x00/au1xxx_psc.h	2005-04-27 13:23:30.000000000 -0500+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/mach-au1x00/au1xxx_psc.h	2005-04-14 20:08:31.969760518 -0500@@ -33,6 +33,8 @@ #ifndef _AU1000_PSC_H_ #define _AU1000_PSC_H_ +#include <linux/config.h>+ /* The PSC base addresses.  */ #ifdef CONFIG_SOC_AU1550 #define PSC0_BASE_ADDR		0xb1a00000diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/mach-db1x00/db1200.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/mach-db1x00/db1200.h--- linux-2.6.12-rc4/include/asm-mips/mach-db1x00/db1200.h	1969-12-31 18:00:00.000000000 -0600+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/mach-db1x00/db1200.h	2005-04-14 20:08:32.001755205 -0500@@ -0,0 +1,214 @@+/*+ * AMD Alchemy DB1200 Referrence Board+ * Board Registers defines.+ *+ * ########################################################################+ *+ *  This program is free software; you can distribute it and/or modify it+ *  under the terms of the GNU General Public License (Version 2) as+ *  published by the Free Software Foundation.+ *+ *  This program is distributed in the hope it will be useful, but WITHOUT+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License+ *  for more details.+ *+ *  You should have received a copy of the GNU General Public License along+ *  with this program; if not, write to the Free Software Foundation, Inc.,+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.+ *+ * ########################################################################+ *+ *+ */+#ifndef __ASM_DB1200_H+#define __ASM_DB1200_H++#include <linux/types.h>++// This is defined in au1000.h with bogus value+#undef AU1X00_EXTERNAL_INT++#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX++/* SPI and SMB are muxed on the Pb1200 board.+   Refer to board documentation.+ */+#define SPI_PSC_BASE        PSC0_BASE_ADDR+#define SMBUS_PSC_BASE      PSC0_BASE_ADDR+/* AC97 and I2S are muxed on the Pb1200 board.+   Refer to board documentation.+ */+#define AC97_PSC_BASE       PSC1_BASE_ADDR+#define I2S_PSC_BASE		PSC1_BASE_ADDR++#define BCSR_KSEG1_ADDR 0xB9800000++typedef volatile struct+{+	/*00*/	u16 whoami;+		u16 reserved0;+	/*04*/	u16 status;+		u16 reserved1;+	/*08*/	u16 switches;+		u16 reserved2;+	/*0C*/	u16 resets;+		u16 reserved3;++	/*10*/	u16 pcmcia;+		u16 reserved4;+	/*14*/	u16 board;+		u16 reserved5;+	/*18*/	u16 disk_leds;+		u16 reserved6;+	/*1C*/	u16 system;+		u16 reserved7;++	/*20*/	u16 intclr;+		u16 reserved8;+	/*24*/	u16 intset;+		u16 reserved9;+	/*28*/	u16 intclr_mask;+		u16 reserved10;+	/*2C*/	u16 intset_mask;+		u16 reserved11;++	/*30*/	u16 sig_status;+		u16 reserved12;+	/*34*/	u16 int_status;+		u16 reserved13;+	/*38*/	u16 reserved14;+		u16 reserved15;+	/*3C*/	u16 reserved16;+		u16 reserved17;++} BCSR;++static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;++/*+ * Register bit definitions for the BCSRs+ */+#define BCSR_WHOAMI_DCID	0x000F+#define BCSR_WHOAMI_CPLD	0x00F0+#define BCSR_WHOAMI_BOARD	0x0F00++#define BCSR_STATUS_PCMCIA0VS	0x0003+#define BCSR_STATUS_PCMCIA1VS	0x000C+#define BCSR_STATUS_SWAPBOOT	0x0040+#define BCSR_STATUS_FLASHBUSY	0x0100+#define BCSR_STATUS_IDECBLID	0x0200+#define BCSR_STATUS_SD0WP		0x0400+#define BCSR_STATUS_U0RXD		0x1000+#define BCSR_STATUS_U1RXD		0x2000++#define BCSR_SWITCHES_OCTAL	0x00FF+#define BCSR_SWITCHES_DIP_1	0x0080+#define BCSR_SWITCHES_DIP_2	0x0040+#define BCSR_SWITCHES_DIP_3	0x0020+#define BCSR_SWITCHES_DIP_4	0x0010+#define BCSR_SWITCHES_DIP_5	0x0008+#define BCSR_SWITCHES_DIP_6	0x0004+#define BCSR_SWITCHES_DIP_7	0x0002+#define BCSR_SWITCHES_DIP_8	0x0001+#define BCSR_SWITCHES_ROTARY	0x0F00++#define BCSR_RESETS_ETH		0x0001+#define BCSR_RESETS_CAMERA	0x0002+#define BCSR_RESETS_DC		0x0004+#define BCSR_RESETS_IDE		0x0008+#define BCSR_RESETS_TV		0x0010+/* not resets but in the same register */+#define BCSR_RESETS_PWMR1mUX 0x0800+#define BCSR_RESETS_PCS0MUX	0x1000+#define BCSR_RESETS_PCS1MUX	0x2000+#define BCSR_RESETS_SPISEL	0x4000++#define BCSR_PCMCIA_PC0VPP	0x0003+#define BCSR_PCMCIA_PC0VCC	0x000C+#define BCSR_PCMCIA_PC0DRVEN	0x0010+#define BCSR_PCMCIA_PC0RST	0x0080+#define BCSR_PCMCIA_PC1VPP	0x0300+#define BCSR_PCMCIA_PC1VCC	0x0C00+#define BCSR_PCMCIA_PC1DRVEN	0x1000+#define BCSR_PCMCIA_PC1RST	0x8000++#define BCSR_BOARD_LCDVEE	0x0001+#define BCSR_BOARD_LCDVDD	0x0002+#define BCSR_BOARD_LCDBL	0x0004+#define BCSR_BOARD_CAMSNAP	0x0010+#define BCSR_BOARD_CAMPWR	0x0020+#define BCSR_BOARD_SD0PWR	0x0040++#define BCSR_LEDS_DECIMALS	0x0003+#define BCSR_LEDS_LED0		0x0100+#define BCSR_LEDS_LED1		0x0200+#define BCSR_LEDS_LED2		0x0400+#define BCSR_LEDS_LED3		0x0800++#define BCSR_SYSTEM_POWEROFF	0x4000+#define BCSR_SYSTEM_RESET	0x8000++/* Bit positions for the different interrupt sources */+#define BCSR_INT_IDE		0x0001+#define BCSR_INT_ETH		0x0002+#define BCSR_INT_PC0		0x0004+#define BCSR_INT_PC0STSCHG	0x0008+#define BCSR_INT_PC1		0x0010+#define BCSR_INT_PC1STSCHG	0x0020+#define BCSR_INT_DC			0x0040+#define BCSR_INT_FLASHBUSY	0x0080+#define BCSR_INT_PC0INSERT	0x0100+#define BCSR_INT_PC0EJECT	0x0200+#define BCSR_INT_PC1INSERT	0x0400+#define BCSR_INT_PC1EJECT	0x0800+#define BCSR_INT_SD0INSERT	0x1000+#define BCSR_INT_SD0EJECT	0x2000++#define AU1XXX_SMC91111_PHYS_ADDR	(0x19000300)+#define AU1XXX_SMC91111_IRQ			DB1200_ETH_INT++#define AU1XXX_ATA_PHYS_ADDR		(0x18800000)+#define AU1XXX_ATA_PHYS_LEN			(0x100)+#define AU1XXX_ATA_REG_OFFSET	(5)+#define AU1XXX_ATA_INT			DB1200_IDE_INT+#define AU1XXX_ATA_DDMA_REQ		DSCR_CMD0_DMA_REQ1;+#define AU1XXX_ATA_RQSIZE		128++#define NAND_PHYS_ADDR   0x20000000++/*+ *	External Interrupts for Pb1200 as of 8/6/2004.+ *   Bit positions in the CPLD registers can be calculated by taking+ *   the interrupt define and subtracting the D