;*****************************************************************************
; File Name:	SPIloop.ASM  (File revision 0.1)
; Project:	F240 Peripheral S/W Library - Test code
; Originator:	J.Crankshaw    (Texas Instruments)
;
; Target Sys:	F240 EVM
;
; Description: This test puts the SPI in "loopback" mode, where
;              the output (SPISIMO) is connected to the input
;              (SPISOMI).  Two eight bit transmissions are performed.
;              The first transfer is used to check the receive function
;              of the SPI and uses the high priority interrupt of the
;              SPI to determine when reception is completed (SPI INT FLAG).
;              The SPIBUF register is not read, and the SPI Status Register
;              (SPISTS) is read in the ISR to verify correct operation.
;              The second transfer is used to check the low priority 
;              interrupt line to determine the second character has been 
;              received.  Because the SPIBUF register was not read after
;              the first interrupt, the second character should generate 
;              a receiver overrun interrupt.  This is checked in the low
;              priority ISR by reading the RECEIVER OVERRUN Flag Bit in
;              the SPI Status Register (SPISTS).  
;
;			The word "BAD" will be in B2 at the end of the test is an 
;			error condition is detected.
;
;              Pass/Fail is verified by checking the contents of B2 RAM.
;              The following values indicate the test passes:
;              
;              60h - 63h : 0000 0055 0040 0005
;              64h - 67h : 0000 00cc 0080 0005
;
; Status:  Assembles and links with no errors. 
;
; Last Update:	2 Feb 98
; ____________________________________________________________________________
; Date of Mod | 		    DESCRIPTION
; ------------|---------------------------------------------------------------
;	 0.1     | create testcase from SMloop1 test program
;	      |
;	      |
;	      |
;*****************************************************************************
;-----------------------------------------------------------------------------
; Debug directives
;-----------------------------------------------------------------------------
		.def	GPR0		;General purpose registers.
		.def	GPR1
		.def	GPR2
		.def	GPR3

     	.include "f240regs.h"

;-----------------------------------------------------------------------------
; Variable Declarations for on chip RAM Blocks
;-----------------------------------------------------------------------------
		.bss	GPR0,1		;General purpose registers.
		.bss	GPR1,1
		.bss	GPR2,1
		.bss	GPR3,1
;-----------------------------------------------------------------------------
; M A C R O - Definitions
;-----------------------------------------------------------------------------
SBIT0	.macro	DMA, MASK	;Clear bit Macro
		LACC	DMA
		AND	#(0FFFFh-MASK)
		SACL	DMA
		.endm

SBIT1	.macro	DMA, MASK	;Set bit Macro
		LACC	DMA
		OR	#MASK
		SACL	DMA
		.endm

KICK_DOG	.macro			;Watchdog reset macro
		LDP	#0100h
		SPLK	#055h, WDKEY
		SPLK	#0AAh, WDKEY
		LDP	#0h
		.endm

RX1_ERLOG .set	B2_SADDR       ; Error log: 0 = pass; BAD = failure
RX_char1  .set B2_SADDR+1h    ; storage for 1st byte received, read in INT1_ISR
INT_FLAG  .set	B2_SADDR+2h	; storage for SPI status register read in INT1_ISR
Ivr1	     .set	B2_SADDR+3h	; IVR generated by SPI in INT1_ISR

RX2_ERLOG .set	B2_SADDR+4h    ; Error log: 0 = pass; BAD = failure
RX_char2  .set B2_SADDR+5h    ; storage for 2nd byte received, read in INT5_ISR
OVER_RUN  .set	B2_SADDR+6h	; storage for SPI status register read in INT5_ISR
Ivr2	     .set	B2_SADDR+7h	; IVR generated by SPI in INT5_ISR

Char1	.set	0055h		; 1st Xmit/rcv byte
Char2	.set	00CCh		; 2nd Xmit/rcv byte

SPIvector	.set	0005h		; SPI interrupt vector offset
;-----------------------------------------------------------------------------
; Vector address declarations
;-----------------------------------------------------------------------------
	  .sect  ".vectors"

RSVECT    B    START	; PM 0    Reset Vector	    1
INT1      B    INT1_ISR	; PM 2    Int level 1	    4
INT2      B    PHANTOM	; PM 4	Int level 2	    5
INT3      B    PHANTOM	; PM 6	Int level 3	    6
INT4      B    PHANTOM	; PM 8	Int level 4	    7
INT5      B    INT5_ISR	; PM A	Int level 5	    8
INT6      B    PHANTOM	; PM C	Int level 6	    9
RESERVED  B    PHANTOM	; PM E	(Analysis Int)    10
SW_INT8   B    PHANTOM	; PM 10   User S/W int	    -
SW_INT9   B    PHANTOM	; PM 12   User S/W int	    -
SW_INT10  B    PHANTOM	; PM 14   User S/W int	    -
SW_INT11  B    PHANTOM	; PM 16   User S/W int	    -
SW_INT12  B    PHANTOM	; PM 18   User S/W int	    -
SW_INT13  B    PHANTOM	; PM 1A   User S/W int	    -
SW_INT14  B    PHANTOM	; PM 1C   User S/W int	    -
SW_INT15  B    PHANTOM	; PM 1E   User S/W int	    -
SW_INT16  B    PHANTOM	; PM 20   User S/W int	    -
TRAP      B    PHANTOM	; PM 22   Trap vector	    -
NMI       B    PHANTOM	; PM 24   Non maskable Int   3
EMU_TRAP  B    PHANTOM	; PM 26   Emulator Trap	    2
SW_INT20  B    PHANTOM	; PM 28   User S/W int	    -
SW_INT21  B    PHANTOM	; PM 2A   User S/W int	    -
SW_INT22  B    PHANTOM	; PM 2C   User S/W int	    -
SW_INT23  B    PHANTOM	; PM 2E   User S/W int	    -

;==============================================================================
; M A I N   C O D E  - starts here
;==============================================================================
	.text
START:
	CLRC	SXM		     ; Clear Sign Extension Mode
	CLRC	OVM		     ; Reset Overflow Mode

* Set Data Page pointer to  page 1 of the peripheral frame
	LDP	#DP_PF1		; Page DP_PF1 includes WET through EINT frames

* initialize WDT registers
     SPLK #06Fh, WDCR    ; clear WDFLAG, Disable WDT, set WDT for 1 second overflow (max)
     SPLK #07h, RTICR    ; clear RTI Flag, set RTI for 1 second overflow (max)

* configure PLL for 10MHz osc, 10MHz SYSCLK and 20MHz CPUCLK
	SPLK	#00B1h,CKCR1	;CLKIN(OSC)=10MHz,CPUCLK=20MHz
	SPLK	#00C3h,CKCR0   ;CLKMD=PLL Enable,SYSCLK=CPUCLK/2,
     
* Clear reset flag bits in SYSSR (PORRST, PLLRST, ILLRST, SWRST, WDRST) 
	LACL	SYSSR		; ACCL <= SYSSR
	AND	#00FFh		; Clear upper 8 bits of SYSSR
	SACL	SYSSR		; Load new value into SYSSR

* Initialize IOP20/CLKOUT pin for use as DSP clock out
	SPLK	#40C8h,SYSCR	;No reset, CLKOUT=CPUCLK, VCCA on

* initialize B2 RAM to zero's.
     LAR  AR1,#B2_SADDR  ; AR1 <= B2 start address 
     MAR  *,AR1          ; use B2 start address for next indirect
     ZAC                 ; ACC <= 0
     RPT  #1fh           ; set repeat counter for 1fh+1=20h or 32 loops
     SACL *+             ; write zeros to B2 RAM

* Call subroutine to initialize SPI and begin character TX
     CALL SPILOOP

     B    END            ; end testcase gracefully

**********************************************************
* Complete main body of code.                            *
**********************************************************

END     NOP                   ; Flush pipeline.
        NOP
        NOP
        NOP
        B      END
*******************************************************************************
*                Subroutines                                                  *
*******************************************************************************
;===========================================================================
; Routine Name: SPILOOP	      Routine Type: SR
;
; Description: This test puts the SPI in "loopback" mode, where
;              the output (SPISIMO) is connected to the input
;              (SPISOMI).  Two eight bit transmissions are performed.
;              The first transfer is used to check the receive function
;              of the SPI and uses the high priority interrupt of the
;              SPI to determine when receive is completed (SPI INT FLAG).
;              The SPIBUF register is not read, and the SPI Status Register
;              (SPISTS) is read in the ISR to verify correct operation.
;              The second transfer is used to check the low priority 
;              interrupt line to determine the second character has been