---------------------------------------------------
-- Screen Display Controller
-- Feb 18 1999
-- "Copyright (c) 2001 Altium Limited"
---------------------------------------------------

------------------------------------------------------------

Library ieee;
Use ieee.std_logic_1164.all;

Library types1;
Use types1.conversions.all;

Entity GenHVSync Is Port
  (
     CLK           : In    std_logic;  -- At 14.32 MHz  (NTSC Frequency X 4)
     Vertical      : In    std_logic_vector(7 downto 0);
     Horizontal    : In    std_logic_vector(8 downto 0);
     vpixel        : Out   std_logic_vector(1 downto 0);
     hpixel        : Out   std_logic_vector(1 downto 0);
     MHz358OSC     : Out   std_logic;
     HSYNC         : Out   std_logic;
     VBLANK        : Out   std_logic
  )
End GenHVSync;

Architecture Structure Of GenHVSync Is

Begin
   --  MHz358OSC = Divide by 4 or CLK

   --  vpixel counts from 1 to 3 on the HSYNCS

   --  hpixel counts from 1 to 3 on the MHz258OSC clock

   --  HSYNC turns on after Horizontal get above 240 is 3 MHz358OSC counts
   --  And stays for 32 counts of MHz358OSC

   --  VSYNC turn on after Vertical gets above 80 and vpixel count and stays for
   --  5-6 HSYNC counts;

End;

Library ieee;
Use ieee.std_logic_1164.all;
-- Use work.ramcntr;

Library types1;
Use types1.conversions.all;

Entity ScrCntr Is Port
   (
     CLK           : In    std_logic;  -- At 14.32 MHz  (NTSC Frequency X 4)
     FPGAMODE1     : In    std_logic;
     FPGAMODE0     : In    std_logic;
     RAMADDR       : Out   std_logic_vector(14 downto 0);  -- For better picture quality we might want
                                                           -- To add the next bit to get 480 resolution
     FPGADAT       : In    std_logic_vector(7 downto 0);
     FRAMOE        : Out   std_logic;
     FRAMWE        : Out   std_logic;
     FRAMRY        : InOut std_logic_vector(3 downto 0);
     FRAMRESET     : Out   std_logic;
     FRAMD         : InOut std_logic_vector(7 downto 0);
     ScreenEnable  : Out   std_logic;
     RedDAC        : Out   std_logic_vector(3 downto 0);
     BlueDAC       : Out   std_logic_vector(3 downto 0);
     GreenDAC      : Out   std_logic_vector(3 downto 0);
     MHz358OSC     : Out   std_logic;
     HSYNC         : Out   std_logic;
     VBLANK        : Out   std_logic
   );
End ScrCntr;
------------------------------------------------------------

------------------------------------------------------------
Architecture Structure Of ScrCntr Is

-- Component Declarations
Component RamRead Port
   (
     CLK           : In    std_logic;
     Enable        : In    std_logic;
     vpixel        : In    std_logic_vector(1 downto 0);
     HorzCount     : In    std_logic_vector(8 downto 0);
     VertCount     : In    std_logic_vector(7 downto 0);
     redout        : Out   std_logic_vector(3 downto 0);
     blueout       : Out   std_logic_vector(3 downto 0);
     greenout      : Out   std_logic_vector(3 downto 0);
     FRAMA         : Out   std_logic_vector(14 downto 0);
     FRAMD         : In    std_logic_vector(7 downto 0);
     FRAMOE        : Out   std_logic;
     ScreenEnable  : Out   std_logic
   );
End Component;
------------------------------------------------------------

Component RamWrite Port
  (
     CLK           : In    std_logic;
     Command       : In    std_logic_vector(1 downto 0);
     FRAMA         : Out   std_logic_vector(14 downto 0);
     FRAMD         : In    std_logic_vector(7 downto 0);
     FRAMOE        : Out   std_logic;
     FRAMWE        : Out   std_logic;
     ScreenEnable  : Out   std_logic
  )
End Component;
------------------------------------------------------------

Component GenHVSync Port
  (
     CLK           : In    std_logic;  -- At 14.32 MHz  (NTSC Frequency X 4)
     Vertical      : In    std_logic_vector(7 downto 0);
     Horizontal    : In    std_logic_vector(7 downto 0);
     vpixel        : Out   std_logic_vector(1 downto 0);
     MHz358OSC     : Out   std_logic;
     HSYNC         : Out   std_logic;
     VBLANK        : Out   std_logic
  )
End Component;
------------------------------------------------------------

-- Signal Declarations

Signal Rst : std_logic;
Signal CountHorz : std_logic_vector(7 downto 0);
Signal CountVert : std_logic_vector(6 downto 0);
Signal ReadEnable : std_logic_vector;

Begin

   Rst <= NOT FPGAMODE1 AND NOT FPGAMODE0;

    process(HSYNC,MHz358OSC)

        variable Q: integer range 0 to 255;
    begin

        if HYSNC = '1' then                -- Asynchronous reset
            Q := 0;
        elsif rising_edge(MHz358OSC) then
            Q := Q + 1;
        end if;

        CountHorz <= to_vector(8,Q);      -- Convert integer to vector
                                          -- for use outside the process.
    end process;

    process(VBLANK,Clk)

        variable Q: integer range 0 to 127;
    begin

        if VBLANK = '1' then                -- Asynchronous reset
            Q := 0;
        elsif rising_edge(Clk) then
            Q := Q + 1;
        end if;

        CountVert <= to_vector(7,Q);     -- Convert integer to vector
                                         -- for use outside the process.
    end process;

    ReadEnable <= !FPGAMODE1 & !FPGAMODE0;
    RamIntr : RamCntr
    Port Map
    (
      CLK          => CLK,
      Enable       => ReadEnable,
      vpixel       => <something that counts horizontal syncs>
      HorzCount    => CountHorz,
      VertCount    => CountVert,
      redout       => RedDAC,
      blueout      => BlueDAC,
      greenout     => GreenDAC,
      FRAMA        => FRAMA,
      FRAMD        => FRAMD,
      FRAMOE       => FRAMOE,
      ScreenEnable => ScreenEnable
    );

End Structure;
------------------------------------------------------------