Protel Design System Design Rule Check
PCB File : \wangjie\work\book\new\myexample\11\4 Port Serial Interface\mypcb.PCBDOC
Date     : 2005-3-14
Time     : 18:35:46

Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (All)
Rule Violations :0

Processing Rule : Testpoint Style (Under Component=Yes) (Disabled)(All)
Rule Violations :0

Processing Rule : Testpoint Usage (Valid =Required, Allow multiple per net=No) (Disabled)(All)
Rule Violations :0

Processing Rule : Solder Mask Expansion (Expansion =50mil) (InPadClass('MTG'))
Rule Violations :0

Processing Rule : Supply Net(s)(InNet('GND'))
Rule Violations :0

Processing Rule : Supply Net(s)(InNet('VCC'))
Rule Violations :0

Processing Rule : Polygon Connect Rule(Relief Connect )(Conductor Width=10mil) (Relief Angle=90 Angle) (Entries=4) (All)
Rule Violations :0

Processing Rule : Power Plane Clearance (Clearance =20mil) (All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Routing Layers(All)
Rule Violations :0

Processing Rule : Solder Mask Expansion (Expansion =4mil) (All)
Rule Violations :0

Processing Rule : Paste Mask Expansion (Expansion =0mil) (All)
Rule Violations :0

Processing Rule : Routing Via (MinHoleWidth=22mil) (MaxHoleWidth=28mil) (PreferredHoleWidth=22mil) (MinWidth=40mil) (MaxWidth=50mil) (PreferedWidth=40mil) (All)
Rule Violations :0

Processing Rule : TRouting Topology Rule(Topology=Shortest) (All)
Rule Violations :0

Processing Rule : TRoutingPriorityRule(Priority=0) (All)
Rule Violations :0

Processing Rule : Paste Mask Expansion (Expansion =-150mil) (InComponent('P1'))
Rule Violations :0

Processing Rule : Routing Corners (Style=45-Degree) (Min Setback=100mil) (Max Setback=100mil) (All)
Rule Violations :0

Processing Rule : Minimum Annular Ring (Minimum=9mil) (All)
   Violation         Pad Free-0(6830mil,9535mil)  MultiLayer  (Annular Ring=-45mil)
Rule Violations :1

Processing Rule : Minimum Annular Ring (Minimum=-90mil) (InPadClass('MTG'))
Rule Violations :0

Processing Rule : Component Clearance Constraint (Gap=10mil) (Disabled)(All),(All)
Rule Violations :0

Processing Rule : Pads and Vias to follow the Drill pairs settings
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=1mil) (Max=140mil) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=18mil) (Max=18mil) (Preferred=18mil) (InNet('+12V_U/P'))
Rule Violations :0

Processing Rule : Width Constraint (Min=18mil) (Max=18mil) (Preferred=18mil) (InNet('-12V_U/P'))
Rule Violations :0

Processing Rule : Width Constraint (Min=18mil) (Max=18mil) (Preferred=18mil) (InNet('-12V'))
Rule Violations :0

Processing Rule : Width Constraint (Min=18mil) (Max=18mil) (Preferred=18mil) (InNet('GND'))
Rule Violations :0

Processing Rule : Width Constraint (Min=18mil) (Max=18mil) (Preferred=18mil) (InNet('VCC'))
Rule Violations :0

Processing Rule : Width Constraint (Min=18mil) (Max=18mil) (Preferred=18mil) (InNet('+12V'))
Rule Violations :0


Violations Detected : 1
Time Elapsed        : 00:00:17