; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 30    ;
;     -- Combinational with no register       ; 6     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 24    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 6     ;
;     -- 2 input functions                    ; 24    ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 9     ;
;     -- arithmetic mode                      ; 21    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 24    ;
; Total logic cells in carry chains           ; 24    ;
; I/O pins                                    ; 52    ;
; Maximum fan-out node                        ; clkin ;
; Maximum fan-out                             ; 24    ;
; Total fan-out                               ; 138   ;
; Average fan-out                             ; 1.68  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |fff                       ; 30 (30)     ; 24           ; 0           ; 0    ; 52   ; 0            ; 6 (6)        ; 0 (0)             ; 24 (24)          ; 24 (24)         ; 0 (0)      ; |fff                ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 24    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 24    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 8:1                ; 8 bits    ; 40 LEs        ; 8 LEs                ; 32 LEs                 ; Yes        ; |fff|var_ss[0]             ;
; 8:1                ; 8 bits    ; 40 LEs        ; 8 LEs                ; 32 LEs                 ; Yes        ; |fff|var_mm[0]             ;
; 8:1                ; 8 bits    ; 40 LEs        ; 8 LEs                ; 32 LEs                 ; Yes        ; |fff|var_hh[0]             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-----------------------------------------------+
; Source assignments for Top-level Entity: |fff ;
+----------------+-------+------+---------------+
; Assignment     ; Value ; From ; To            ;
+----------------+-------+------+---------------+
; POWER_UP_LEVEL ; Low   ; -    ; var_ss[0]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_ss[1]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_ss[2]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_ss[3]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_ss[4]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_ss[5]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_ss[6]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_ss[7]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_mm[0]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_mm[1]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_mm[2]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_mm[3]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_mm[4]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_mm[5]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_mm[6]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_mm[7]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_hh[0]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_hh[1]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_hh[2]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_hh[3]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_hh[4]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_hh[5]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_hh[6]     ;
; POWER_UP_LEVEL ; Low   ; -    ; var_hh[7]     ;
+----------------+-------+------+---------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Fri Aug 03 16:04:40 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fff -c fff
Info: Found 2 design units, including 1 entities, in source file fff.vhd
    Info: Found design unit 1: fff-arc
    Info: Found entity 1: fff
Info: Elaborating entity "fff" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at fff.vhd(30): signal "clkin" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Implemented 82 device resources after synthesis - the final resource count might be different
    Info: Implemented 28 input pins
    Info: Implemented 24 output pins
    Info: Implemented 30 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Aug 03 16:04:42 2007
    Info: Elapsed time: 00:00:03