?? lf2407regs.h
字號(hào):
; TI2000系列的頭文件直接調(diào)用
;*************************************************************
; File Name: x24x.h
; Description: x24x Peripheral Registers + other useful definitions
; Target: x240/3, x/2407
;====================================================================;; Select the target device by setting 1
;--------------------------------------------------------------
x240 .set 0 ; C/F240
x243 .set 1 ; C/F243
x2407 .set 0 ; F2407
;For F2407EVM only
;Select PLL multiplication ratio
x2_PLL .set 1
x4_PLL .set 0
;--------------------------------------------------------------
; On Chip Periperal Register Definitions
;--------------------------------------------------------------
;全局變量寄存器和cpu中斷寄存器
IMR .set 0004h ; Int Mask
GREG .set 0005h ; Global memory allocation
IFR .set 0006h ; Int Flag
ABRPT .set 01fh ; Analysis BreakPoint
WSGR .set 0FFFFh ; Wait State Control (IO space mapped)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;系統(tǒng)通用模塊寄存器
PIRQR0 .set 7010h ; Peripheral Interrupt Request Reg0(241/2/3,240x only)
PIRQR1 .set 7011h ; Peripheral Interrupt Request Reg1(241/2/3,240x only)
PIRQR2 .set 7012h ; Peripheral Interrupt Request Reg2(240x)
PIACKR0 .set 07014h
PIACKR1 .set 07015h
PIACKR2 .set 07016h
SYSCR .set 7018h ; System Control (X240 only)
SYSSR .set 701Ah ; System Status (X240 only)
SYSIVR .set 701Eh ; System Int Vector (X240 only)
SSCR .set 7018h ; System Stat & Contr (X241/2/3 only)
PIVR .set 701Eh ; Periph Int Vector (X241/2/3 only)
SCSR1 .set 07018h ; System contr & stat 1 (240x only)
SCSR2 .set 07019h ; System contr & stat 2 (240x only)
DINR .set 0701Ch ; Device Identification Register
PIVR .SET 0701EH
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; PLL configuration registers - X240 only
CKCR0 .set 702ah ; PLL Clock Control 0 (X240 only)
CKCR1 .set 702ch ; PLL Clock Control 1 (X240 only)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;WD程序監(jiān)視控制寄存器 / Real Time Int(RTI) / Phase Lock Loop(PLL) Registers
RTI_CNTR .set 07021h ; RTI Counter reg
WDCNTR .set 07023h ; WD Counter reg
WDKEY .set 07025h ; WD Key reg
RTI_CNTL .set 07027h ; RTI Control reg
WDCR .set 07029h ; WD Control reg
PLL_CNTL1 .set 0702Bh ; PLL control reg 1
PLL_CNTL2 .set 0702Dh ; PLL control reg 2
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;串行外圍接口 (SPI) Registers
SPICCR .set 07040h ;SPI Config Control Reg 1
SPICTL .set 07041h ;SPI Operation Control Reg 2
SPISTS .set 07042h ;SPI Status Reg
SPIBRR .set 07044h ;SPI Baud rate control reg
SPIEMU .set 07046h ;SPI Emulation buffer reg
SPIRXBUF .set 07047h ;SPI Serial Input buffer reg
SPITXBUF .SET 07048H
SPIDAT .set 07049h ;SPI Serial Data reg
SPI_PC1 .set 0704Dh ;SPI Port control reg1
SPI_PC2 .set 0704Eh ;SPI Port control reg2
SPIPRI .set 0704Fh ;SPI Priority control reg
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;串行通訊接口 (SCI) Registers
SCICCR .set 07050h ;SCI Comms Control Reg
SCICTL1 .set 07051h ;SCI Control Reg 1
SCIHBAUD .set 07052h ;SCI Baud rate control
SCILBAUD .set 07053h ;SCI Baud rate control
SCICTL2 .set 07054h ;SCI Control Reg 2
SCIRXST .set 07055h ;SCI Receive status reg
SCIRXEMU .set 07056h ;SCI EMU data buffer
SCIRXBUF .set 07057h ;SCI Receive data buffer
SCITXBUF .set 07059h ;SCI Transmit data buffer
SCI_PORT_C1 .set 0705Dh ;SCI Port control reg1
SCI_PORT_C2 .set 0705Eh ;SCI Port control reg2
SCIPRI .set 0705Fh ;SCI Priority control reg
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; 外部中斷寄存器
XINT1CR .set 7070h ; Int1 config. X241/2/3, (X240x only)
XINT2CR .set 7071h ; Int2 config. X241/2/3, (X240x only)
XINT1CR240 .set 7070h ; Int1 (type A) config (X240 only)
XINT2CR240 .set 7078h ; Int2 (type C) config (X240 only)
XINT3CR240 .set 707Ah ; Int3 (type C) config (X240 only)
NMICR .set 7072h ; NMI (type A) config (X240 only)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;數(shù)據(jù)I/O控制寄存器
OCRA .set 07090h ; Output Control A
MCRA .set 07090h ;I/O Mux Control Reg A
OCRB .set 07092h ; Output Control B
MCRB .set 07092h ;I/O Mux Control Reg B
OCRC .set 07094h ; Output control C (X240x only)
MCRC .set 07094h
ISRA .set 7094h ; Input Status A (X240 only)
ISRB .set 7096h ; Input Status B (X240 only)
IPSRA .set 07094h ;Input Status Reg A
IPSRB .set 07096h ;Input Status Reg B
PADATDIR .set 07098h ; I/O port A Data & Direction
PBDATDIR .set 0709Ah ; I/O port B Data & Direction
PCDATDIR .set 0709Ch ; I/O port C Data & Direction
PDDATDIR .set 0709Eh ;I/O port D Data & Direction reg.
PEDATDIR .set 07095h ; I/O port D Data & Direction
PFDATDIR .set 07096h ; I/O port D Data & Direction
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;--------------------------------------------------------------
;模數(shù)轉(zhuǎn)換ADC寄存器
;ADC Register declarations - x240x
;--------------------------------------------------------------
ADCTRL1 .set 070A0h ;ADC Control reg 1
ADCTRL2 .set 070A1h ;ADC Control reg 2
MAXCONV .set 070A2h ;Maximum conversions in sequence
CHSELSEQ1 .set 070A3h ;Channel select fields: Results 3,2,1,0
CHSELSEQ2 .set 070A4h ;Channel select fields: Results 7,6,5,4
CHSELSEQ3 .set 070A5h ;Channel select fields: Results 11,10,9,8
CHSELSEQ4 .set 070A6h ;Channel select fields: Results 15,14,13,12
AUTO_SEQ_SR .set 070A7h ;Auto-sequence status Register
RESULT0 .set 070A8h ;Conversion result 0
RESULT1 .set 070A9h ;Conversion result 1
RESULT2 .set 070AAh ;Conversion result 2
RESULT3 .set 070ABh ;Conversion result 3
RESULT4 .set 070ACh ;Conversion result 4
RESULT5 .set 070ADh ;Conversion result 5
RESULT6 .set 070AEh ;Conversion result 6
RESULT7 .set 070AFh ;Conversion result 7
RESULT8 .set 070B0h ;Conversion result 8
RESULT9 .set 070B1h ;Conversion result 9
RESULT10 .set 070B2h ;Conversion result 10
RESULT11 .set 070B3h ;Conversion result 11
RESULT12 .set 070B4h ;Conversion result 12
RESULT13 .set 070B5h ;Conversion result 13
RESULT14 .set 070B6h ;Conversion result 14
RESULT15 .set 070B7h ;Conversion result 15
CALIBRATION .set 070B8h ;Calibration Register
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;通用（GP）定時(shí)器配置控制寄存器－－－EVA
GPTCONA .set 07400h ; General Timer Control
T1CNT .set 07401h ; T1 Counter
T1CMPR .set 07402h ; T1 Compare value
T1PR .set 07403h ; T1 Period
T1CON .set 07404h ; T1 Control
T2CNT .set 07405h ; T2 Counter
T2CMPR .set 07406h ; T2 Compare value
T2PR .set 07407h ; T2 Period
T2CON .set 07408h ; T2 Control
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;比較單元寄存器－－－事件管理器A
COMCONA .set 07411h ; Compare Control
ACTRA .set 07413h ; Compare Output Action Control (240 Only)
DBTCONA .set 07415h ; Dead Band Control
CMPR1 .set 07417h ; Compare value 1
CMPR2 .set 07418h ; Compare value 2
CMPR3 .set 07419h ; Compare value 3
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;捕捉和正交編碼寄存器－－－事件管理器A
CAPCONA .set 07420h ; Capture Control
CAPFIFOA .set 07422h ; Capture FIFO1-3/4 Status
CAP1FIFO .set 07423h ; Capture 1 FIFO Top
CAP2FIFO .set 07424h ; Capture 2 FIFO Top
CAP3FIFO .set 07425h ; Capture 3 FIFO Top
CAP1FBOT .set 07427h ; Capture 1 FIFO Bottom (240x only)
CAP2FBOT .set 07428h ; Capture 2 FIFO Bottom (240x only)
CAP3FBOT .set 07429h ; Capture 3 FIFO Bottom (240x only)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;事件管理器A中斷控制寄存器
EVAIMRA .set 0742Ch ; Group A Int Mask
EVAIMRB .set 0742Dh ; Group B Int Mask
EVAIMRC .set 0742Eh ; Group C Int Mask
EVAIFRA .set 0742Fh ; Group A Int Flag
EVAIFRB .set 07430h ; Group B Int Flag
EVAIFRC .set 07431h ; Group C Int Flag
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;通用（GP）定時(shí)器配置控制寄存器－－－EVB
GPTCONB .set 07500h ; General Timer Control
T3CNT .set 07501h ; T1 Counter
T3CMPR .set 07502h ; T1 Comp value
T3PR .set 07503h ; T1 Period
T3CON .set 07504h ; T1 Control
T4CNT .set 07505h ; T2 Counter
T4CMPR .set 07506h ; T2 Comp value
T4PR .set 07507h ; T2 Period
T4CON .set 07508h ; T2 Control
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;比較單元－－－EVB
COMCONB .set 07511h ; Compare Control
ACTRB .set 07513h ; Compare Output Action Control
DBTCONB .set 07515h ; Dead Band Control
CMPR4 .set 07517h ; Comp value 4
CMPR5 .set 07518h ; Comp value 5
CMPR6 .set 07519h ; Comp value 6
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;捕捉和正交編碼寄存器－－－事件管理器B
CAPCONB .set 07520h ; Capture Control
CAPFIFOB .set 07522h ; Capture FIFO4-6 Status
CAP4FIFO .set 07523h ; Capture 4 FIFO Top
CAP5FIFO .set 07524h ; Capture 5 FIFO Top
CAP6FIFO .set 07525h ; Capture 6 FIFO Top
CAP4FBOT .set 07527h ; Capture 4 FIFO Bottom
CAP5FBOT .set 07528h ; Capture 5 FIFO Bottom
CAP6FBOT .set 07529h ; Capture 6 FIFO Bottom
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;事件管理器EVB中斷控制器
EVBIMRA .set 0752ch ; Group A Int Mask
EVBIMRB .set 0752dh ; Group B Int Mask
EVBIMRC .set 0752eh ; Group C Int Mask
EVBIFRA .set 0752fh ; Group A Int Flag
EVBIFRB .set 07530h ; Group B Int Flag
EVBIFRC .set 07531h ; Group C Int Flag
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;程序存儲(chǔ)器空間－－－Flash寄存器
;PMPC .SET 0H
;CTRL .SET 01H
;WADDR .SET 2H
;WDATA .SET 3H
;TCR .SET 4H
;ENAB .SET 5H
;SETC .SET 6H
;I/O存儲(chǔ)空間
FCMR .SET 0FF0FH
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;數(shù)據(jù)存儲(chǔ)器塊地址
B0_SADDR .set 00200h ;Block B0 start address
B0_EADDR .set 002FFh ;Block B0 end address
B1_SADDR .set 00300h ;Block B1 start address
B1_EADDR .set 003FFh ;Block B1 end address
B2_SADDR .set 00060h ;Block B2 start address
B2_EADDR .set 0007Fh ;Block B2 end address
XDATA_SADDR .SET 08000H ;外部數(shù)據(jù)空間開始地址
XDATA_EADDR .SET 0FFFFH ;外部數(shù)據(jù)空間結(jié)束地址
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;經(jīng)常使用的數(shù)據(jù)頁
DP_B2 .SET 0 ;頁0數(shù)據(jù)空間
DP_B01 .SET 4 ;頁4 B0(0200h/0080h)
DP_B02 .SET 5 ;頁5 B0(0280h/0080h)
DP_B11 .SET 6 ;頁6 B0(0300h/0080h)
DP_B12 .SET 7 ;頁7 B0(0380h/0080h)
DP_SARAM1 .SET 16 ;頁1 SARAM(0800h/0080h)
DP_SARAM2 .SET 26 ;頁2 SARAM(0D00h/0080h)
DP_SARAM3 .SET 18 ;頁3 SARAM(0900h/0080h)
DP_SARAM4 .SET 19 ;頁4 SARAM(0980h/0080h)
DP_PF1 .SET 224 ;頁1 外設(shè)幀文件(7000h/0080h)
DP_PF2 .SET 225 ;頁2 外設(shè)幀文件(7080h/0080h)
DP_PF3 .SET 226 ;頁3 外設(shè)幀文件(7100h/0080h)
DP_PF4 .SET 227 ;頁4 外設(shè)幀文件(7180h/0080h)
DP_PF5 .SET 228 ;頁5 外設(shè)幀文件(7200h/0080h)
DP_EVA .SET 232 ;頁0 事件管理器－EVA文件(7400/0080h)0xe8h
DP_EVB .SET 234 ;頁0 事件管理器－EVB文件(7500/0080h)0xeah
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;位測試指令的位代碼
BIT15 .set 0000h ;Bit Code for 15
BIT14 .set 0001h ;Bit Code for 14
BIT13 .set 0002h ;Bit Code for 13
BIT12 .set 0003h ;Bit Code for 12
BIT11 .set 0004h ;Bit Code for 11
BIT10 .set 0005h ;Bit Code for 10
BIT9 .set 0006h ;Bit Code for 9
BIT8 .set 0007h ;Bit Code for 8
BIT7 .set 0008h ;Bit Code for 7
BIT6 .set 0009h ;Bit Code for 6
BIT5 .set 000Ah ;Bit Code for 5
BIT4 .set 000Bh ;Bit Code for 4
BIT3 .set 000Ch ;Bit Code for 3
BIT2 .set 000Dh ;Bit Code for 2
BIT1 .set 000Eh ;Bit Code for 1
BIT0 .set 000Fh ;Bit Code for 0
;用SBIT0和SBIT1宏屏蔽位
B15_MSK .set 8000h ;Bit Mask for 15
B14_MSK .set 4000h ;Bit Mask for 14
B13_MSK .set 2000h ;Bit Mask for 13
B12_MSK .set 1000h ;Bit Mask for 12
B11_MSK .set 0800h ;Bit Mask for 11
B10_MSK .set 0400h ;Bit Mask for 10
B9_MSK .set 0200h ;Bit Mask for 9
B8_MSK .set 0100h ;Bit Mask for 8
B7_MSK .set 0080h ;Bit Mask for 7
B6_MSK .set 0040h ;Bit Mask for 6
B5_MSK .set 0020h ;Bit Mask for 5
B4_MSK .set 0010h ;Bit Mask for 4
B3_MSK .set 0008h ;Bit Mask for 3
B2_MSK .set 0004h ;Bit Mask for 2
B1_MSK .set 0002h ;Bit Mask for 1
B0_MSK .set 0001h ;Bit Mask for 0
;External Data Space Registers
EXTDATA .set 8000h
;---------------------------------------------------------------------
; M A C R O - Definitions
;---------------------------------------------------------------------
SBIT0 .macro DMA,MASK ; Clear bit Macro
LACC DMA
AND #(0FFFFh-MASK)
SACL DMA
.endm
SBIT1 .macro DMA,MASK ; Set bit Macro
LACC DMA
OR #MASK
SACL DMA
.endm
KICK_DOG .macro ;Watchdog reset macro
LDP #WD_KEY>>7
SPLK #05555h,WD_KEY
SPLK #0AAAAh,WD_KEY
.endm
POINT_PG0 .macro
LDP #00h
.endm
POINT_B0 .macro
LDP #04h
.endm
POINT_PF1 .macro
LDP #0E0h
.endm
POINT_PF2 .macro
LDP #0E1h
.endm
POINT_EV .macro
LDP #0E8h
.endm
wd_rst_1 .set 055h ; watchdog timer reset string
wd_rst_2 .set 0aah ; watchdog timer reset string
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