?? untitled.c
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/*
** ###################################################################
** This code is generated by the Device Initialization Tool.
** It is overwritten during code generation.
** USER MODIFICATION ARE PRESERVED ONLY INSIDE INTERRUPT SERVICE ROUTINES
**
** Project : xs
** Processor : MC68HC908JL16CFJE
** Version : Bean 01.046, Driver 01.00, CPU db: 2.87.077
** Datasheet : MC68HC908JL16 Rev. 1.1 11/2005
** Date/Time : 2007-8-7, 17:22
** Abstract :
** This bean "MC68HC908JL16_32FA" provides initialization of the
** CPU core and shared peripherals.
** Settings :
** Clock setting
** External clock : 9.8304 MHz
** CPU mode selection : 0
** Initialization interrupt priority : 1
** Stop instruction enabled : no
** LVI module : yes
**
** Source clock : Main clock frequency / 1
** Internal bus clock : 2.4576 MHz
** Contents :
** Function "MCU_init" initializes selected peripherals
**
** (c) Copyright UNIS, spol. s r.o. 1997-2006
** UNIS, spol s r.o.
** Jundrovska 33
** 624 00 Brno
** Czech Republic
** http : www.processorexpert.com
** mail : info@processorexpert.com
** ###################################################################
*/
#include <MC68HC908JL16.h> /* I/O map for MC68HC908JL16CFJE */
#define CGM_DELAY 0x27FFUL
/*
** ===================================================================
** Method : MCU_init (bean MC68HC908JL16_32FA)
**
** Description :
** Device initialization code for selected peripherals.
** ===================================================================
*/
void MCU_init(void)
{
/*** ### MC68HC908JL16_32FA "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
/* System clock initialization */
/* Common initialization of the write once registers */
/* CONFIG1: COPRS=1,LVID=0,SSREC=0,STOP=0,COPD=0 */
CONFIG1 = 0x80;
/* CONFIG2: IRQPUD=0,LVIT1=1,LVIT0=0,IICSEL=0,STOP_ICLKDIS=0 */
CONFIG2 = 0x10;
/* Common initialization of the CPU registers */
/* ### Init_TIM init code */
/* T1SC: TOF=0,TOIE=0,TSTOP=1,TRST=1,PS2=0,PS1=0,PS0=0 */
T1SC = 0x30; /* Stop and reset counter */
T1MOD = 0x1333; /* Period value setting */
(void)(T1SC == 0); /* Overflow int. flag clearing (first part) */
/* T1SC: TOF=0,TOIE=0,TSTOP=1,TRST=0,PS2=0,PS1=0,PS0=0 */
T1SC = 0x20; /* Int. flag clearing (2nd part) and timer contr. register setting */
/* ### Init_TIM init code */
/* T2SC: TOF=0,TOIE=0,TSTOP=1,TRST=1,PS2=0,PS1=0,PS0=0 */
T2SC = 0x30; /* Stop and reset counter */
T2MOD = 0x95FF; /* Period value setting */
(void)(T2SC == 0); /* Overflow int. flag clearing (first part) */
/* T2SC: TOF=0,TOIE=0,TSTOP=1,TRST=0,PS2=1,PS1=1,PS0=0 */
T2SC = 0x26; /* Int. flag clearing (2nd part) and timer contr. register setting */
/* ### Init_COP init code */
COPCTL = 0xFF; /* Clear WatchDog counter */
/* ### */
asm CLI; /* Enable interrupts */
} /*MCU_init*/
/*
** ===================================================================
** Interrupt handler : isrINT_TIM2Ovr
**
** Description :
** User interrupt service routine.
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
__interrupt void isrINT_TIM2Ovr(void)
{
/* Write your interrupt code here ... */
}
/* end of isrINT_TIM2Ovr */
/*
** ===================================================================
** Interrupt handler : isrINT_TIM1Ovr
**
** Description :
** User interrupt service routine.
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
__interrupt void isrINT_TIM1Ovr(void)
{
/* Write your interrupt code here ... */
}
/* end of isrINT_TIM1Ovr */
/* Initialization of the CPU registers in FLASH */
/* MOR: OSCSEL=1 */
const unsigned char MOR_INIT @0x0000FFD0 = 0xFF;
#define UNASSIGNED_ISR 0xFFFF /* Unassigned interrupt service routine */
extern void _Startup(void); /* reset interrupt service routine */
void (* const _vect[])() @0xFFDE = { // Interrupt vector table
UNASSIGNED_ISR, /* Int.no. 0 INT_ADC (at FFDE) Unassigned */
UNASSIGNED_ISR, /* Int.no. 1 INT_KBI (at FFE0) Unassigned */
UNASSIGNED_ISR, /* Int.no. 2 INT_SCITransmit (at FFE2) Unassigned */
UNASSIGNED_ISR, /* Int.no. 3 INT_SCIReceive (at FFE4) Unassigned */
UNASSIGNED_ISR, /* Int.no. 4 INT_SCIError (at FFE6) Unassigned */
UNASSIGNED_ISR, /* Int.no. 5 INT_MMIIC (at FFE8) Unassigned */
UNASSIGNED_ISR, /* Int.no. 6 Reserved6 (at FFEA) Unassigned */
isrINT_TIM2Ovr, /* Int.no. 7 INT_TIM2Ovr (at FFEC) Used */
UNASSIGNED_ISR, /* Int.no. 8 INT_TIM2CH1 (at FFEE) Unassigned */
UNASSIGNED_ISR, /* Int.no. 9 INT_TIM2CH0 (at FFF0) Unassigned */
isrINT_TIM1Ovr, /* Int.no. 10 INT_TIM1Ovr (at FFF2) Used */
UNASSIGNED_ISR, /* Int.no. 11 INT_TIM1CH1 (at FFF4) Unassigned */
UNASSIGNED_ISR, /* Int.no. 12 INT_TIM1CH0 (at FFF6) Unassigned */
UNASSIGNED_ISR, /* Int.no. 13 Reserved13 (at FFF8) Unassigned */
UNASSIGNED_ISR, /* Int.no. 14 INT_IRQ1 (at FFFA) Unassigned */
UNASSIGNED_ISR, /* Int.no. 15 INT_SWI (at FFFC) Unassigned */
_Startup /* Int.no. 16 INT_RESET (at FFFE) Reset vector */
};
/* END */
/*
** ###################################################################
**
** This file was created by UNIS Processor Expert 2.99 [03.85]
** for the Freescale HC08 series of microcontrollers.
**
** ###################################################################
*/
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