-- ********************************************************************
--
-- Owner:	Xilinx Inc.
-- File:  	nand_interface.vhd
--
-- Purpose: 	Interface for the AMD AM30LV0064D UltraNAND Flash and
--		Samsung K9F4008W0A memory devices.  Decodes the lower 
--		address bits of the system bus to decode commands and set 
--		or clear interface signals.
--		This device includes a RESET input to force WP# asserted 
--		on power transitions. RESET is high until Vcc is valid
--		and goes high when supply power ramps down.
--
-- *********************************************************************

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


entity NAND_INTERFACE is

	port(	
		-- Input Signals to CPLD
		write_n		: in 	STD_LOGIC;			-- System Write Enable
		read_n		: in 	STD_LOGIC;			-- System Read Enable	
		port_addr	: in 	STD_LOGIC_VECTOR (3 downto 0);	-- Address input to select port
		ce_n		: in 	STD_LOGIC;			-- Chip Enable for the interface and UltraNAND 
		ry_byn		: in 	STD_LOGIC;			-- RY/BY# input from UltraNAND 
		reset		: in 	STD_LOGIC;			-- RESET - high for reset and power transitions
		com_lat_n	: in 	STD_LOGIC;			-- COM_LAT from test bench to negate CLE 
									-- during command write cycle
			
		-- Output signals from CPLD
		ready 		: out 	STD_LOGIC;			-- Allows system to read RY/BY# pin state 
		cle		: out 	STD_LOGIC;			-- Command Latch Enable to UltraNAND 
		ale		: out 	STD_LOGIC;			-- Address Latch Enable to UltraNAND 
		se_n		: out 	STD_LOGIC;			-- Spare Area Enable to UltraNAND 
		wp_n 		: out 	STD_LOGIC;			-- Write Protect to UltraNAND 
		outce_n		: out 	STD_LOGIC;			-- Chip Enable to UltraNAND 	
		we_n 		: out 	STD_LOGIC;			-- Write Enable to UltraNAND 
		re_n		: out 	STD_LOGIC			-- Read Enable to UltraNAND 

		);
	
end NAND_INTERFACE;


architecture BEHAVIOR of NAND_INTERFACE is 

constant RESET_ACTIVE : STD_LOGIC := '1';

-- Define port address signals
signal port0	: STD_LOGIC;
signal port1	: STD_LOGIC;
signal port2	: STD_LOGIC;
signal port3	: STD_LOGIC;
signal port4	: STD_LOGIC;
signal port5	: STD_LOGIC;
signal port6	: STD_LOGIC;
signal port7	: STD_LOGIC;
signal port8	: STD_LOGIC;
signal port9	: STD_LOGIC;
signal porta	: STD_LOGIC;
signal portb	: STD_LOGIC;
signal portc	: STD_LOGIC;
signal portd	: STD_LOGIC;
signal porte	: STD_LOGIC;
signal portf	: STD_LOGIC;

-- Create internal signals
signal se_n_int		: STD_LOGIC;
signal ale_int		: STD_LOGIC;
signal wp_n_int 	: STD_LOGIC;
signal outce_n_int 	: STD_LOGIC;


begin

	-- ********************** SIGNAL ASSIGNMENTS *************************

	-- Assign output signals
	se_n <= se_n_int;
	ale <= ale_int;
	wp_n <= wp_n_int;
	outce_n <= outce_n_int;

	-- Data read/write port
	port0 <= (not ce_n) and (not port_addr(3)) and (not port_addr(2)) and (not port_addr(1)) 
		and (not port_addr(0)); 	

	-- CLE write port 
	port1 <= (not ce_n) and (not port_addr(3)) and (not port_addr(2)) 
		and (not port_addr(1)) and port_addr(0);

	-- Used to set ALE
	port2 <= (not ce_n) and (not port_addr(3)) and (not port_addr(2)) 
		and port_addr(1) and (not port_addr(0));
	
	-- Used to clear ALE
	port3 <= (not ce_n) and (not port_addr(3)) and (not port_addr(2)) 
		and port_addr(1) and port_addr(0);

	-- Used to set SE# 
	port4 <= (not ce_n) and (not port_addr(3)) and port_addr(2) 
		and (not port_addr(1)) and (not port_addr(0)); 
	
	-- Used to clear SE#
	port5 <= (not ce_n) and (not port_addr(3)) and port_addr(2) 
		and (not port_addr(1)) and port_addr(0); 	
	
	-- Used to set WP# 
	port6 <= (not ce_n) and (not port_addr(3)) and port_addr(2) 
		and port_addr(1) and (not port_addr(0)); 	
	
	-- Used to clear WP# 
	port7 <= (not ce_n) and (not port_addr(3)) and port_addr(2) 
		and port_addr(1) and port_addr(0); 	
	
	-- Used to set OUTCE# 
	port8 <= (not ce_n) and port_addr(3) and (not port_addr(2)) 
		and (not port_addr(1)) and (not port_addr(0)); 

	-- Used to clear OUTCE# 
	port9 <= (not ce_n) and port_addr(3) and (not port_addr(2)) 
		and (not port_addr(1)) and port_addr(0); 	

	-- No Function
	porta <= (not ce_n) and port_addr(3) and (not port_addr(2)) and port_addr(1) 
		and (not port_addr(0)); 
	portb <= (not ce_n) and port_addr(3) and (not port_addr(2)) and port_addr(1) 
		and port_addr(0); 
	portc <= (not ce_n) and port_addr(3) and port_addr(2) and (not port_addr(1)) 
		and (not port_addr(0)); 	
	portd <= (not ce_n) and port_addr(3) and port_addr(2) and (not port_addr(1)) 
		and port_addr(0); 
	porte <= (not ce_n) and port_addr(3) and port_addr(2) and port_addr(1) 
		and (not port_addr(0)); 	

	-- To read RY/BY# state 
	portf <= (not ce_n) and port_addr(3) and port_addr(2) and port_addr(1) 
		and port_addr(0); 	

	-- Assert CLE on all port1 accesses 
	cle <= port1;			       
	
	-- Drive WE# to UltraNAND for port0 or port1 
	we_n <= not ((not write_n) and ( port0 or (port1 and (not com_lat_n))));
	
	
	-- Drive REor to UltraNAND for port0 only 
	re_n <= not ((not read_n) and port0); 	
	
		
	-- ********************** PROCESS: ALE_SIG ******************************
	-- Purpose: Assert ALE signal
	ALE_SIG: process (reset, write_n, port2, port3)
	begin	
		-- Reset Condition
		if (reset = RESET_ACTIVE) then
			ale_int <= '0';
		
		-- Latch ALE on write to PORT2
		elsif (write_n = '0') and (port2 = '1') then
			ale_int <= '1';
		
		-- Clear on write to PORT3
		elsif (write_n = '0') and (port3 = '1') then
			ale_int <= '0';
		
		-- Transparent latch cover term
		else
			ale_int <= ale_int;
			
		end if;
	
	end process ALE_SIG;
	
	
	-- ********************** PROCESS: SEN_SIG ******************************
	-- Purpose: Assert SE# signal
	SEN_SIG: process (reset, write_n, port4, port5)
	begin	
		-- Reset Condition
		if (reset = RESET_ACTIVE) then
			se_n_int <= '1';
		
		-- Latch SE# on write to PORT4
		elsif (write_n = '0') and (port4 = '1') then
			se_n_int <= '0';
		
		-- Clear on write to PORT5
		elsif (write_n = '0') and (port5 = '1') then
			se_n_int <= '1';
		
		-- Transparent latch cover term
		else
			se_n_int <= se_n_int;
			
		end if;
	
	end process SEN_SIG;
	
	
	-- ********************** PROCESS: WPN_SIG ******************************
	-- Purpose: Assert WP# signal
	WPN_SIG: process (reset, write_n, port6, port7)
	begin	
		-- Reset Condition
		if (reset = RESET_ACTIVE) then
			wp_n_int <= '0';
		
		-- Latch WP# on write to PORT6
		elsif (write_n = '0') and (port6 = '1') then
			wp_n_int <= '0';
		
		-- Clear on write to PORT7
		elsif (write_n = '0') and (port7 = '1') then
			wp_n_int <= '1';
		
		-- Transparent latch cover term
		else
			wp_n_int <= wp_n_int;
			
		end if;
	
	end process WPN_SIG;
		
								
	-- ********************* PROCESS: OUTCE_SIG *****************************
	-- Purpose: Assert OUTCE# signal
	OUTCE_SIG: process (reset, write_n, port8, port9)
	begin	
		-- Reset Condition
		if (reset = RESET_ACTIVE) then
			outce_n_int <= '1';
		
		-- Set OUTCE# (low) on write to port8
		elsif (write_n = '0') and (port8 = '1') then
			outce_n_int <= '0';
		
		-- Clear OUTCE# (high) on write to port9
		elsif (write_n = '0') and (port9 = '1') then
			outce_n_int <= '1';
		
		-- Transparent latch cover term
		else
			outce_n_int <= outce_n_int;
			
		end if;
	
	end process OUTCE_SIG;
	
		
	-- ********************** PROCESS: READY_SIG ******************************
	-- Purpose: Assert ready signal
	READY_SIG: process (portf, read_n)
	begin	
		-- READY is only driven during a PORTF read
		-- READY shows the state of RY/BY# 
		if (portf = '1') and (read_n = '0') then
			ready <= ry_byn;
		else
			ready <= 'Z';
		end if;
	
	end process READY_SIG;

 
 end BEHAVIOR;