Release 7.1i - xst H.38Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.42 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.42 s | Elapsed : 0.00 / 0.00 s --> Reading design: bmg.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "bmg.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "bmg"Output Format                      : NGCTarget Device                      : xc3s2000-5-fg676---- Source OptionsTop Module Name                    : bmgAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : bmg.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yesenable_auto_floorplanning          : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "branch_gen.v"Module <branch_gen> compiledCompiling verilog file "dist_calc.v"Module <dist_calc> compiledCompiling verilog file "bmg.v"Module <bmg> compiledNo errors in compilationAnalysis of file <"bmg.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <bmg>.Module <bmg> is correct for synthesis. Analyzing module <branch_gen>.Module <branch_gen> is correct for synthesis. Analyzing module <dist_calc>.Module <dist_calc> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================INFO:Xst:1304 - Contents of register <CodeRegister> in unit <bmg> never changes during circuit operation. The register is replaced by logic.Synthesizing Unit <dist_calc>.    Related source file is "dist_calc.v".    Found 1-bit xor2 for signal <OutputDistance<0>>.    Found 1-bit xor2 for signal <LS>.    Found 1-bit xor2 for signal <MS>.Unit <dist_calc> synthesized.Synthesizing Unit <branch_gen>.    Related source file is "branch_gen.v".    Found 2-bit xor7 for signal <EncOut>.    Summary:	inferred   2 Xor(s).Unit <branch_gen> synthesized.Synthesizing Unit <bmg>.    Related source file is "bmg.v".WARNING:Xst:647 - Input <Clock2> is never used.WARNING:Xst:647 - Input <Code> is never used.WARNING:Xst:1780 - Signal <wA> is never used or assigned.WARNING:Xst:1780 - Signal <wB> is never used or assigned.WARNING:Xst:646 - Signal <B1> is assigned but never used.WARNING:Xst:646 - Signal <B3> is assigned but never used.WARNING:Xst:646 - Signal <B5> is assigned but never used.WARNING:Xst:646 - Signal <B7> is assigned but never used.Unit <bmg> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Xors                             : 32 1-bit xor2                        : 24 1-bit xor7                        : 8==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================WARNING:Xst:1989 - Unit <bmg>: instances <EN2/Mxor_EncOut<0>>, <EN4/Mxor_EncOut<0>> of unit <LPM_XOR7_1> are equivalent, second instance is removedWARNING:Xst:1989 - Unit <bmg>: instances <EN2/Mxor_EncOut<0>>, <EN0/Mxor_EncOut<0>> of unit <LPM_XOR7_1> are equivalent, second instance is removedWARNING:Xst:1989 - Unit <bmg>: instances <EN2/Mxor_EncOut<0>>, <EN6/Mxor_EncOut<0>> of unit <LPM_XOR7_1> are equivalent, second instance is removedWARNING:Xst:1989 - Unit <bmg>: instances <EN4/Mxor_EncOut<1>>, <EN0/Mxor_EncOut<1>> of unit <LPM_XOR7_1> are equivalent, second instance is removedWARNING:Xst:1989 - Unit <bmg>: instances <EN6/Mxor_EncOut<1>>, <EN2/Mxor_EncOut<1>> of unit <LPM_XOR7_1> are equivalent, second instance is removedOptimizing unit <bmg> ...Optimizing unit <dist_calc> ...Loading device for application Rf_Device from file '3s2000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block bmg, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : bmg.ngrTop Level Output File Name         : bmgOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 24Macro Statistics :# Xors                             : 8#      1-bit xor7                  : 8Cell Usage :# BELS                             : 6#      INV                         : 2#      LUT4                        : 4# IO Buffers                       : 20#      IBUF                        : 4#      OBUF                        : 16=========================================================================Device utilization summary:---------------------------Selected Device : 3s2000fg676-5  Number of Slices:                       2  out of  20480     0%   Number of 4 input LUTs:                 4  out of  40960     0%   Number of bonded IOBs:                 24  out of    489     4%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5   Minimum period: No path found   Minimum input arrival time before clock: No path found   Maximum output required time after clock: No path found   Maximum combinational path delay: 8.107nsTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default path analysis  Total number of paths / destination ports: 40 / 16-------------------------------------------------------------------------Delay:               8.107ns (Levels of Logic = 3)  Source:            ACSSegment<2> (PAD)  Destination:       Distance<15> (PAD)  Data Path: ACSSegment<2> to Distance<15>                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     IBUF:I->O            10   0.715   1.259  ACSSegment_2_IBUF (ACSSegment_2_IBUF)     LUT4:I0->O            2   0.479   0.745  HD2/_n000411 (Distance_5_OBUF)     OBUF:I->O                 4.909          Distance_5_OBUF (Distance<5>)    ----------------------------------------    Total                      8.107ns (6.103ns logic, 2.004ns route)                                       (75.3% logic, 24.7% route)=========================================================================CPU : 4.81 / 5.28 s | Elapsed : 5.00 / 5.00 s --> Total memory usage is 128052 kilobytesNumber of errors   :    0 (   0 filtered)Number of warnings :   13 (   0 filtered)Number of infos    :    1 (   0 filtered)