Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "branch_gen.v"Module <branch_gen> compiledNo errors in compilationAnalysis of file <"branch_gen.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <branch_gen>.Module <branch_gen> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <branch_gen>.    Related source file is "branch_gen.v".    Found 2-bit xor7 for signal <EncOut>.    Summary:	inferred   2 Xor(s).Unit <branch_gen> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Xors                             : 2 1-bit xor7                        : 2==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <branch_gen> ...Loading device for application Rf_Device from file '3s2000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block branch_gen, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 3s2000fg676-5  Number of Slices:                       6  out of  20480     0%   Number of 4 input LUTs:                10  out of  40960     0%   Number of bonded IOBs:                 23  out of    489     4%  =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5   Minimum period: No path found   Minimum input arrival time before clock: No path found   Maximum output required time after clock: No path found   Maximum combinational path delay: 10.669ns=========================================================================

Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "dist_calc.v"Module <dist_calc> compiledNo errors in compilationAnalysis of file <"dist_calc.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <dist_calc>.Module <dist_calc> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <dist_calc>.    Related source file is "dist_calc.v".    Found 1-bit xor2 for signal <OutputDistance<0>>.    Found 1-bit xor2 for signal <LS>.    Found 1-bit xor2 for signal <MS>.Unit <dist_calc> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Xors                             : 3 1-bit xor2                        : 3==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <dist_calc> ...Loading device for application Rf_Device from file '3s2000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block dist_calc, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 3s2000fg676-5  Number of Slices:                       1  out of  20480     0%   Number of 4 input LUTs:                 2  out of  40960     0%   Number of bonded IOBs:                  6  out of    489     1%  =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5   Minimum period: No path found   Minimum input arrival time before clock: No path found   Maximum output required time after clock: No path found   Maximum combinational path delay: 7.824ns=========================================================================

Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "branch_gen.v"Module <branch_gen> compiledCompiling verilog file "dist_calc.v"Module <dist_calc> compiledCompiling verilog file "bmg.v"Module <bmg> compiledNo errors in compilationAnalysis of file <"bmg.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <bmg>.Module <bmg> is correct for synthesis. Analyzing module <branch_gen>.Module <branch_gen> is correct for synthesis. Analyzing module <dist_calc>.Module <dist_calc> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================INFO:Xst:1304 - Contents of register <CodeRegister> in unit <bmg> never changes during circuit operation. The register is replaced by logic.Synthesizing Unit <dist_calc>.    Related source file is "dist_calc.v".    Found 1-bit xor2 for signal <OutputDistance<0>>.    Found 1-bit xor2 for signal <LS>.    Found 1-bit xor2 for signal <MS>.Unit <dist_calc> synthesized.Synthesizing Unit <branch_gen>.    Related source file is "branch_gen.v".    Found 2-bit xor7 for signal <EncOut>.    Summary:	inferred   2 Xor(s).Unit <branch_gen> synthesized.Synthesizing Unit <bmg>.    Related source file is "bmg.v".WARNING:Xst:647 - Input <Clock2> is never used.WARNING:Xst:647 - Input <Code> is never used.WARNING:Xst:1780 - Signal <wA> is never used or assigned.WARNING:Xst:1780 - Signal <wB> is never used or assigned.WARNING:Xst:646 - Signal <B1> is assigned but never used.WARNING:Xst:646 - Signal <B3> is assigned but never used.WARNING:Xst:646 - Signal <B5> is assigned but never used.WARNING:Xst:646 - Signal <B7> is assigned but never used.Unit <bmg> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Xors                             : 32 1-bit xor2                        : 24 1-bit xor7                        : 8==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================WARNING:Xst:1989 - Unit <bmg>: instances <EN2/Mxor_EncOut<0>>, <EN4/Mxor_EncOut<0>> of unit <LPM_XOR7_1> are equivalent, second instance is removedWARNING:Xst:1989 - Unit <bmg>: instances <EN2/Mxor_EncOut<0>>, <EN0/Mxor_EncOut<0>> of unit <LPM_XOR7_1> are equivalent, second instance is removedWARNING:Xst:1989 - Unit <bmg>: instances <EN2/Mxor_EncOut<0>>, <EN6/Mxor_EncOut<0>> of unit <LPM_XOR7_1> are equivalent, second instance is removedWARNING:Xst:1989 - Unit <bmg>: instances <EN4/Mxor_EncOut<1>>, <EN0/Mxor_EncOut<1>> of unit <LPM_XOR7_1> are equivalent, second instance is removedWARNING:Xst:1989 - Unit <bmg>: instances <EN6/Mxor_EncOut<1>>, <EN2/Mxor_EncOut<1>> of unit <LPM_XOR7_1> are equivalent, second instance is removedOptimizing unit <bmg> ...Optimizing unit <dist_calc> ...Loading device for application Rf_Device from file '3s2000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block bmg, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 3s2000fg676-5  Number of Slices:                       2  out of  20480     0%   Number of 4 input LUTs:                 4  out of  40960     0%   Number of bonded IOBs:                 24  out of    489     4%  =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5   Minimum period: No path found   Minimum input arrival time before clock: No path found   Maximum output required time after clock: No path found   Maximum combinational path delay: 8.107ns=========================================================================