?? ti_cc_spi.c
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//----------------------------------------------------------------------------
// Description: This file contains functions that allow the MSP430 device to
// access the SPI interface of the CC1100/CC2500. There are multiple
// instances of each function; the one to be compiled is selected by the
// system variable TI_CC_RF_SER_INTF, defined in "TI_CC_hardware_board.h".
//
// MSP430/CC1100-2500 Interface Code Library v1.0
//
// K. Quiring
// Texas Instruments, Inc.
// July 2006
// IAR Embedded Workbench v3.41
//----------------------------------------------------------------------------
#include "include.h"
#include "TI_CC_spi.h"
//----------------------------------------------------------------------------
// void TI_CC_SPISetup(void)
//
// DESCRIPTION:
// Configures the assigned interface to function as a SPI port and
// initializes it.
//----------------------------------------------------------------------------
// void TI_CC_SPIWriteReg(char addr, char value)
//
// DESCRIPTION:
// Writes "value" to a single configuration register at address "addr".
//----------------------------------------------------------------------------
// void TI_CC_SPIWriteBurstReg(char addr, char *buffer, char count)
//
// DESCRIPTION:
// Writes values to multiple configuration registers, the first register being
// at address "addr". First data byte is at "buffer", and both addr and
// buffer are incremented sequentially (within the CCxxxx and MSP430,
// respectively) until "count" writes have been performed.
//----------------------------------------------------------------------------
// char TI_CC_SPIReadReg(char addr)
//
// DESCRIPTION:
// Reads a single configuration register at address "addr" and returns the
// value read.
//----------------------------------------------------------------------------
// void TI_CC_SPIReadBurstReg(char addr, char *buffer, char count)
//
// DESCRIPTION:
// Reads multiple configuration registers, the first register being at address
// "addr". Values read are deposited sequentially starting at address
// "buffer", until "count" registers have been read.
//----------------------------------------------------------------------------
// char TI_CC_SPIReadStatus(char addr)
//
// DESCRIPTION:
// Special read function for reading status registers. Reads status register
// at register "addr" and returns the value read.
//----------------------------------------------------------------------------
// void TI_CC_SPIStrobe(char strobe)
//
// DESCRIPTION:
// Special write function for writing to command strobe registers. Writes
// to the strobe at address "addr".
//----------------------------------------------------------------------------
// Delay function. # of CPU cycles delayed is similar to "cycles". Specifically,
// it's ((cycles-15) % 6) + 15. Not exact, but gives a sense of the real-time
// delay. Also, if MCLK ~1MHz, "cycles" is similar to # of useconds delayed.
void TI_CC_Wait(unsigned int cycles)
{
while(cycles>15) // 15 cycles consumed by overhead
cycles = cycles - 6; // 6 cycles consumed each iteration
}
// SPI port functions
#if TI_CC_RF_SER_INTF == TI_CC_SER_INTF_USART0
void TI_CC_SPISetup(void)
{
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_CSn_PxDIR |= TI_CC_CSn_PIN; // /CS disable
ME1 |= USPIE0; // Enable USART0 SPI mode
UCTL0 |= CHAR + SYNC + MM; // 8-bit SPI Master **SWRST**
UTCTL0 |= CKPH + SSEL1 + SSEL0 + STC; // SMCLK, 3-pin mode
UBR00 = 0x02; // UCLK/2
UBR10 = 0x00; // 0
UMCTL0 = 0x00; // No modulation
TI_CC_SPI_USART0_PxSEL |= TI_CC_SPI_USART0_SIMO | TI_CC_SPI_USART0_SOMI | TI_CC_SPI_USART0_UCLK;
// SPI option select
TI_CC_SPI_USART0_PxDIR |= TI_CC_SPI_USART0_SIMO + TI_CC_SPI_USART0_UCLK;
// SPI TX out direction
UCTL0 &= ~SWRST; // Initialize USART state machine
}
void TI_CC_SPIWriteReg(char addr, char value)
{
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART0_PxIN&TI_CC_SPI_USART0_SOMI);// Wait for CCxxxx ready
IFG1 &= ~URXIFG0; // Clear flag from first dummy byte
U0TXBUF = addr; // Send address
while (!(IFG1&URXIFG0)); // Wait for TX to finish
IFG1 &= ~URXIFG0; // Clear flag from first dummy byte
U0TXBUF = value; // Send value
while (!(IFG1&URXIFG0)); // Wait for end of data TX
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
void TI_CC_SPIWriteBurstReg(char addr, char *buffer, char count)
{
char i;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART0_PxIN&TI_CC_SPI_USART0_SOMI);// Wait for CCxxxx ready
U0TXBUF = addr | TI_CCxxx0_WRITE_BURST; // Send address
while (!(IFG1&UTXIFG0)); // Wait for TX to finish
for (i = 0; i < count; i++)
{
U0TXBUF = buffer[i]; // Send data
while (!(IFG1&UTXIFG0)); // Wait for TX to finish
}
IFG1 &= ~URXIFG0;
while(!(IFG1&URXIFG0));
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
char TI_CC_SPIReadReg(char addr)
{
char x;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART0_PxIN&TI_CC_SPI_USART0_SOMI);// Wait for CCxxxx ready
U0TXBUF = (addr | TI_CCxxx0_READ_SINGLE); // Send address
while (!(IFG1&URXIFG0)); // Wait for TX to finish
IFG1 &= ~URXIFG0; // Clear flag set during last write
U0TXBUF = 0; // Dummy write so we can read data
while (!(IFG1&URXIFG0)); // Wait for RX to finish
x = U0RXBUF; // Read data
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
return x;
}
void TI_CC_SPIReadBurstReg(char addr, char *buffer, char count)
{
unsigned int i;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART0_PxIN&TI_CC_SPI_USART0_SOMI);// Wait for CCxxxx ready
IFG1 &= ~URXIFG0; // Clear flag
U0TXBUF = (addr | TI_CCxxx0_READ_BURST); // Send address
while (!(IFG1&UTXIFG0)); // Wait for TXBUF ready
U0TXBUF = 0; // Dummy write to read 1st data byte
// Addr byte is now being TX'ed, with dummy byte to follow immediately after
while (!(IFG1&URXIFG0)); // Wait for end of addr byte TX
IFG1 &= ~URXIFG0; // Clear flag
while (!(IFG1&URXIFG0)); // Wait for end of 1st data byte TX
// First data byte now in RXBUF
for (i = 0; i < (count-1); i++)
{
U0TXBUF = 0; //Initiate next data RX, meanwhile..
buffer[i] = U0RXBUF; // Store data from last data RX
while (!(IFG1&URXIFG0)); // Wait for end of data RX
}
buffer[count-1] = U0RXBUF; // Store last RX byte in buffer
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
// For status/strobe addresses, the BURST bit selects between status registers
// and command strobes.
char TI_CC_SPIReadStatus(char addr)
{
char x;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART0_PxIN & TI_CC_SPI_USART0_SOMI);// Wait for CCxxxx ready
IFG1 &= ~URXIFG0; // Clear flag set during last write
U0TXBUF = (addr | TI_CCxxx0_READ_BURST); // Send address
while (!(IFG1&URXIFG0)); // Wait for TX to finish
IFG1 &= ~URXIFG0; // Clear flag set during last write
U0TXBUF = 0; // Dummy write so we can read data
while (!(IFG1&URXIFG0)); // Wait for RX to finish
x = U0RXBUF; // Read data
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
return x;
}
void TI_CC_SPIStrobe(char strobe)
{
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART0_PxIN&TI_CC_SPI_USART0_SOMI);// Wait for CCxxxx ready
U0TXBUF = strobe; // Send strobe
// Strobe addr is now being TX'ed
IFG1 &= ~URXIFG0; // Clear flag
while (!(IFG1&URXIFG0)); // Wait for end of addr TX
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
void TI_CC_PowerupResetCCxxxx(void)
{
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_Wait(30);
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN;
TI_CC_Wait(30);
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_Wait(45);
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART0_PxIN&TI_CC_SPI_USART0_SOMI);// Wait for CCxxxx ready
U0TXBUF = TI_CCxxx0_SRES; // Send strobe
// Strobe addr is now being TX'ed
IFG1 &= ~URXIFG0; // Clear flag
while (!(IFG1&URXIFG0)); // Wait for end of addr TX
while (TI_CC_SPI_USART0_PxIN&TI_CC_SPI_USART0_SOMI);
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
#elif TI_CC_RF_SER_INTF == TI_CC_SER_INTF_USART1
void TI_CC_SPISetup(void)
{
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_CSn_PxDIR |= TI_CC_CSn_PIN; // /CS disable
ME2 |= USPIE1; // Enable USART1 SPI mode
UCTL1 |= CHAR + SYNC + MM; // 8-bit SPI Master **SWRST**
UTCTL1 |= CKPL + SSEL1 + SSEL0 + STC; // SMCLK, 3-pin mode
UBR01 = 0x02; // UCLK/2
UBR11 = 0x00; // 0
UMCTL1 = 0x00; // No modulation
TI_CC_SPI_USART1_PxSEL |= TI_CC_SPI_USART1_SIMO | TI_CC_SPI_USART1_SOMI | TI_CC_SPI_USART1_UCLK;
// SPI option select
TI_CC_SPI_USART1_PxDIR |= TI_CC_SPI_USART1_SIMO + TI_CC_SPI_USART1_UCLK;
// SPI TXD out direction
UCTL1 &= ~SWRST; // Initialize USART state machine
}
void TI_CC_SPIWriteReg(char addr, char value)
{
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART1_PxIN&TI_CC_SPI_USART1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~URXIFG1; // Clear flag
U1TXBUF = addr; // Send address
while (!(IFG2&URXIFG1)); // Wait for TX to finish
IFG2 &= ~URXIFG1; // Clear flag
U1TXBUF = value; // Load data for TX after addr
while (!(IFG2&URXIFG1)); // Wait for end of addr TX
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
void TI_CC_SPIWriteBurstReg(char addr, char *buffer, char count)
{
char i;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART1_PxIN&TI_CC_SPI_USART1_SOMI);// Wait for CCxxxx ready
U1TXBUF = addr | TI_CCxxx0_WRITE_BURST; // Send address
while (!(IFG2&UTXIFG1)); // Wait for TX to finish
for (i = 0; i < count; i++)
{
U1TXBUF = buffer[i]; // Send data
while (!(IFG2&UTXIFG1)); // Wait for TX to finish
}
IFG2 &= ~URXIFG1;
while(!(IFG2&URXIFG1));
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
char TI_CC_SPIReadReg(char addr)
{
char x;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART1_PxIN&TI_CC_SPI_USART1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~URXIFG1; // Clear flag set during addr TX
U1TXBUF = (addr | TI_CCxxx0_READ_SINGLE); // Send address
while (!(IFG2&URXIFG1)); // Wait for TXBUF ready
IFG2 &= ~URXIFG1; // Clear flag set during addr TX
U1TXBUF = 0; // Load dummy byte for TX after addr
while (!(IFG2&URXIFG1)); // Wait for end of dummy byte TX
x = U1RXBUF; // Read data
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
return x;
}
void TI_CC_SPIReadBurstReg(char addr, char *buffer, char count)
{
unsigned int i;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART1_PxIN&TI_CC_SPI_USART1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~URXIFG1; // Clear flag
U1TXBUF = (addr | TI_CCxxx0_READ_BURST); // Send address
while (!(IFG2&UTXIFG1)); // Wait for TXBUF ready
U1TXBUF = 0; // Dummy write to read 1st data byte
// Addr byte is now being TX'ed, with dummy byte to follow immediately after
while (!(IFG2&URXIFG1)); // Wait for end of addr byte TX
IFG2 &= ~URXIFG1; // Clear flag
while (!(IFG2&URXIFG1)); // Wait for end of 1st data byte TX
// First data byte now in RXBUF
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