?? control.rpt
字號:
_ _ _ _ _ _ N _ _ _ _ _ _ C _ _ _ _ _ C _ _ _ N C E L C N N _ C _ _ _ _ _ _ C _ _ _ _ _ _ C _ _ _ _ _ E
A A A A A A D A A A A A A C A A D D D C D D D D C K U D D D C D D D D D D C D D D D D D C D D D D D S
D D D D D D D D D D D D I D D A A A I A A A I 5 _ A I A A A A A A I A A A A A A I A A A A A E
D D D D D D D D D D D D O D D T T T N T T T N 0 C T O T T T T T T N T T T T T T O T T T T T R
R R R R R R R R R R R R R R A A A T A A A T M L A A A A A A A T A A A A A A A A A A A V
0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 K 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 E
0 1 2 3 4 5 6 7 8 9 0 1 2 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: f:\jlh\cotrol\control.rpt
control
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A5 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A6 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A7 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A8 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A9 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A12 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A13 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 2/22( 9%)
A14 5/ 8( 62%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
A16 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 2/22( 9%)
A19 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
B2 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
B3 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
B4 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
B12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
B14 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
B15 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
B16 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
B22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 2/22( 9%)
B25 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
B27 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 2/22( 9%)
C4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
C12 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 1/2 1/2 1/22( 4%)
C13 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
C14 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
C16 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
C19 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 9/22( 40%)
C22 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 8/22( 36%)
C23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 5/22( 22%)
C24 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 4/22( 18%)
C25 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C26 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 1/2 4/22( 18%)
C27 6/ 8( 75%) 6/ 8( 75%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
C29 4/ 8( 50%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 7/22( 31%)
C30 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 6/22( 27%)
C31 4/ 8( 50%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
C32 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 14/22( 63%)
C33 7/ 8( 87%) 3/ 8( 37%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
C34 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
C35 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 2/22( 9%)
C36 8/ 8(100%) 7/ 8( 87%) 1/ 8( 12%) 1/2 0/2 10/22( 45%)
D9 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
D10 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 17/22( 77%)
D11 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
D12 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
D13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
D14 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
D16 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 17/22( 77%)
D21 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
D22 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
D23 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
D24 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
E14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
E16 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
E17 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
E18 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
E19 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
E20 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
F19 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 7/22( 31%)
F21 6/ 8( 75%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
F24 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 1/22( 4%)
F26 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
F27 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
F28 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
F31 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 4/22( 18%)
F33 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
F34 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 6/22( 27%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 121/141 ( 85%)
Total logic cells used: 292/1728 ( 16%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 2.78/4 ( 69%)
Total fan-in: 813/6912 ( 11%)
Total input pins required: 32
Total input I/O cell registers required: 0
Total output pins required: 47
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 48
Total reserved pins required 0
Total logic cells required: 292
Total flipflops required: 164
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Logic cells inserted for fitting: 1
Synthesized logic cells: 55/1728 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 2 2 2 2 2 1 0 1 8 5 0 8 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35/0
B: 0 2 2 2 0 0 0 0 0 0 0 1 0 8 8 2 0 0 0 0 0 0 8 0 0 3 0 8 0 0 0 0 0 0 0 0 0 44/0
C: 0 0 0 1 0 0 0 0 0 0 0 8 2 2 0 1 0 0 0 8 0 0 8 8 8 1 8 6 0 4 8 4 8 7 3 8 8 111/0
D: 0 0 0 0 0 0 0 0 2 8 1 2 1 8 0 8 0 0 0 0 0 2 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 36/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 6 0 0 2 0 8 8 1 0 0 8 0 8 8 0 0 57/0
Total: 0 2 2 3 2 2 2 2 4 9 1 12 11 24 8 20 2 1 0 19 2 9 17 10 11 4 16 22 1 4 8 12 8 15 11 8 8 292/0
Device-Specific Information: f:\jlh\cotrol\control.rpt
control
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
69 - - - 23 BIDIR ^ 0 1 0 0 A_DATA00
70 - - - 22 BIDIR ^ 0 1 0 0 A_DATA01
71 - - - 21 BIDIR ^ 0 1 0 0 A_DATA02
73 - - - 20 BIDIR ^ 0 1 0 0 A_DATA03
74 - - - 20 BIDIR ^ 0 1 0 1 A_DATA04
75 - - - 19 BIDIR ^ 0 1 0 1 A_DATA05
83 - - - 17 BIDIR ^ 0 1 0 1 A_DATA06
85 - - - 16 BIDIR ^ 0 1 0 1 A_DATA07
86 - - - 15 BIDIR ^ 0 1 0 0 A_DATA08
87 - - - 14 BIDIR ^ 0 1 0 0 A_DATA09
88 - - - 14 BIDIR ^ 0 1 0 0 A_DATA10
89 - - - 13 BIDIR ^ 0 1 0 0 A_DATA11
90 - - - 12 BIDIR ^ 0 1 0 1 A_DATA12
92 - - - 11 BIDIR ^ 0 1 0 1 A_DATA13
93 - - - 10 BIDIR ^ 0 1 0 1 A_DATA14
94 - - - 09 BIDIR ^ 0 1 0 1 A_DATA15
95 - - - 09 BIDIR ^ 0 1 0 0 A_DATA16
96 - - - 08 BIDIR ^ 0 1 0 0 A_DATA17
97 - - - 07 BIDIR ^ 0 1 0 0 A_DATA18
99 - - - 06 BIDIR ^ 0 1 0 0 A_DATA19
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