?? control.rpt
字號:
100 - - - 05 BIDIR ^ 0 1 0 1 A_DATA20
101 - - - 04 BIDIR ^ 0 1 0 1 A_DATA21
102 - - - 03 BIDIR ^ 0 1 0 1 A_DATA22
103 - - - 02 BIDIR ^ 0 1 0 1 A_DATA23
192 - - - 24 BIDIR ^ 0 1 0 0 B_DATA00
191 - - - 23 BIDIR ^ 0 1 0 0 B_DATA01
190 - - - 22 BIDIR ^ 0 1 0 0 B_DATA02
189 - - - 21 BIDIR ^ 0 1 0 0 B_DATA03
187 - - - 20 BIDIR ^ 0 1 0 1 B_DATA04
186 - - - 19 BIDIR ^ 0 1 0 1 B_DATA05
180 - - - 18 BIDIR ^ 0 1 0 1 B_DATA06
179 - - - 17 BIDIR ^ 0 1 0 1 B_DATA07
177 - - - 16 BIDIR ^ 0 1 0 0 B_DATA08
176 - - - 15 BIDIR ^ 0 1 0 0 B_DATA09
175 - - - 14 BIDIR ^ 0 1 0 0 B_DATA10
174 - - - 14 BIDIR ^ 0 1 0 0 B_DATA11
173 - - - 13 BIDIR ^ 0 1 0 1 B_DATA12
172 - - - 12 BIDIR ^ 0 1 0 1 B_DATA13
170 - - - 11 BIDIR ^ 0 1 0 1 B_DATA14
169 - - - 10 BIDIR ^ 0 1 0 1 B_DATA15
168 - - - 09 BIDIR ^ 0 1 0 0 B_DATA16
167 - - - 08 BIDIR ^ 0 1 0 0 B_DATA17
116 - - F -- BIDIR ^ 0 1 0 0 B_DATA18
115 - - F -- BIDIR ^ 0 1 0 0 B_DATA19
114 - - F -- BIDIR ^ 0 1 0 1 B_DATA20
113 - - F -- BIDIR ^ 0 1 0 1 B_DATA21
112 - - F -- BIDIR ^ 0 1 0 1 B_DATA22
111 - - F -- BIDIR ^ 0 1 0 1 B_DATA23
29 - - D -- INPUT ^ 0 0 0 2 BLUE00
30 - - D -- INPUT ^ 0 0 0 2 BLUE01
31 - - D -- INPUT ^ 0 0 0 2 BLUE02
36 - - E -- INPUT ^ 0 0 0 2 BLUE03
37 - - E -- INPUT ^ 0 0 0 2 BLUE04
38 - - E -- INPUT ^ 0 0 0 2 BLUE05
39 - - E -- INPUT ^ 0 0 0 2 BLUE06
40 - - E -- INPUT ^ 0 0 0 2 BLUE07
79 - - - -- INPUT G ^ 0 0 0 0 CLK50M
183 - - - -- INPUT G ^ 0 0 0 2 DCLK
78 - - - -- INPUT ^ 0 0 0 13 DE
15 - - B -- INPUT ^ 0 0 0 2 GREEN00
17 - - C -- INPUT ^ 0 0 0 2 GREEN01
18 - - C -- INPUT ^ 0 0 0 2 GREEN02
24 - - C -- INPUT ^ 0 0 0 2 GREEN03
25 - - D -- INPUT ^ 0 0 0 2 GREEN04
26 - - D -- INPUT ^ 0 0 0 2 GREEN05
27 - - D -- INPUT ^ 0 0 0 2 GREEN06
28 - - D -- INPUT ^ 0 0 0 2 GREEN07
182 - - - -- INPUT G ^ 0 0 0 0 HS
80 - - - -- INPUT G ^ 0 0 0 0 MCU_CLK
47 - - F -- INPUT ^ 0 0 0 1 MCU_DATA
163 - - - 06 INPUT ^ 0 0 0 8 MCU_LATCH
7 - - A -- INPUT ^ 0 0 0 2 RED00
8 - - A -- INPUT ^ 0 0 0 2 RED01
9 - - A -- INPUT ^ 0 0 0 2 RED02
10 - - A -- INPUT ^ 0 0 0 2 RED03
11 - - A -- INPUT ^ 0 0 0 2 RED04
12 - - B -- INPUT ^ 0 0 0 2 RED05
13 - - B -- INPUT ^ 0 0 0 2 RED06
14 - - B -- INPUT ^ 0 0 0 2 RED07
184 - - - -- INPUT G ^ 0 0 0 0 VS
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\jlh\cotrol\control.rpt
control
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
53 - - - 36 OUTPUT 0 1 0 0 A_ADDR00
54 - - - 35 OUTPUT 0 1 0 0 A_ADDR01
55 - - - 34 OUTPUT 0 1 0 0 A_ADDR02
56 - - - 33 OUTPUT 0 1 0 0 A_ADDR03
57 - - - 32 OUTPUT 0 1 0 0 A_ADDR04
58 - - - 31 OUTPUT 0 1 0 0 A_ADDR05
60 - - - 30 OUTPUT 0 1 0 0 A_ADDR06
61 - - - 29 OUTPUT 0 1 0 0 A_ADDR07
62 - - - 28 OUTPUT 0 1 0 0 A_ADDR08
63 - - - 27 OUTPUT 0 1 0 0 A_ADDR09
64 - - - 26 OUTPUT 0 1 0 0 A_ADDR10
65 - - - 26 OUTPUT 0 1 0 0 A_ADDR11
67 - - - 25 OUTPUT 0 1 0 0 A_ADDR12
68 - - - 24 OUTPUT 0 0 0 0 A_ADDR13
69 - - - 23 TRI 0 1 0 0 A_DATA00
70 - - - 22 TRI 0 1 0 0 A_DATA01
71 - - - 21 TRI 0 1 0 0 A_DATA02
73 - - - 20 TRI 0 1 0 0 A_DATA03
74 - - - 20 TRI 0 1 0 1 A_DATA04
75 - - - 19 TRI 0 1 0 1 A_DATA05
83 - - - 17 TRI 0 1 0 1 A_DATA06
85 - - - 16 TRI 0 1 0 1 A_DATA07
86 - - - 15 TRI 0 1 0 0 A_DATA08
87 - - - 14 TRI 0 1 0 0 A_DATA09
88 - - - 14 TRI 0 1 0 0 A_DATA10
89 - - - 13 TRI 0 1 0 0 A_DATA11
90 - - - 12 TRI 0 1 0 1 A_DATA12
92 - - - 11 TRI 0 1 0 1 A_DATA13
93 - - - 10 TRI 0 1 0 1 A_DATA14
94 - - - 09 TRI 0 1 0 1 A_DATA15
95 - - - 09 TRI 0 1 0 0 A_DATA16
96 - - - 08 TRI 0 1 0 0 A_DATA17
97 - - - 07 TRI 0 1 0 0 A_DATA18
99 - - - 06 TRI 0 1 0 0 A_DATA19
100 - - - 05 TRI 0 1 0 1 A_DATA20
101 - - - 04 TRI 0 1 0 1 A_DATA21
102 - - - 03 TRI 0 1 0 1 A_DATA22
103 - - - 02 TRI 0 1 0 1 A_DATA23
41 - - E -- OUTPUT 0 1 0 0 A_OE
44 - - F -- OUTPUT 0 1 0 0 A_WE
208 - - - 36 OUTPUT 0 1 0 0 B_ADDR00
207 - - - 35 OUTPUT 0 1 0 0 B_ADDR01
206 - - - 34 OUTPUT 0 1 0 0 B_ADDR02
205 - - - 34 OUTPUT 0 1 0 0 B_ADDR03
204 - - - 33 OUTPUT 0 1 0 0 B_ADDR04
203 - - - 32 OUTPUT 0 1 0 0 B_ADDR05
202 - - - 31 OUTPUT 0 1 0 0 B_ADDR06
200 - - - 30 OUTPUT 0 1 0 0 B_ADDR07
199 - - - 29 OUTPUT 0 1 0 0 B_ADDR08
198 - - - 28 OUTPUT 0 1 0 0 B_ADDR09
197 - - - 28 OUTPUT 0 1 0 0 B_ADDR10
196 - - - 27 OUTPUT 0 1 0 0 B_ADDR11
195 - - - 26 OUTPUT 0 1 0 0 B_ADDR12
193 - - - 25 OUTPUT 0 0 0 0 B_ADDR13
144 - - B -- OUTPUT 0 1 0 0 BDATA0
192 - - - 24 TRI 0 1 0 0 B_DATA00
150 - - A -- OUTPUT 0 1 0 0 BDATA1
191 - - - 23 TRI 0 1 0 0 B_DATA01
147 - - A -- OUTPUT 0 1 0 0 BDATA2
190 - - - 22 TRI 0 1 0 0 B_DATA02
122 - - E -- OUTPUT 0 1 0 0 BDATA3
189 - - - 21 TRI 0 1 0 0 B_DATA03
187 - - - 20 TRI 0 1 0 1 B_DATA04
186 - - - 19 TRI 0 1 0 1 B_DATA05
180 - - - 18 TRI 0 1 0 1 B_DATA06
179 - - - 17 TRI 0 1 0 1 B_DATA07
177 - - - 16 TRI 0 1 0 0 B_DATA08
176 - - - 15 TRI 0 1 0 0 B_DATA09
175 - - - 14 TRI 0 1 0 0 B_DATA10
174 - - - 14 TRI 0 1 0 0 B_DATA11
173 - - - 13 TRI 0 1 0 1 B_DATA12
172 - - - 12 TRI 0 1 0 1 B_DATA13
170 - - - 11 TRI 0 1 0 1 B_DATA14
169 - - - 10 TRI 0 1 0 1 B_DATA15
168 - - - 09 TRI 0 1 0 0 B_DATA16
167 - - - 08 TRI 0 1 0 0 B_DATA17
116 - - F -- TRI 0 1 0 0 B_DATA18
115 - - F -- TRI 0 1 0 0 B_DATA19
114 - - F -- TRI 0 1 0 1 B_DATA20
113 - - F -- TRI 0 1 0 1 B_DATA21
112 - - F -- TRI 0 1 0 1 B_DATA22
111 - - F -- TRI 0 1 0 1 B_DATA23
45 - - F -- OUTPUT 0 1 0 0 B_OE
46 - - F -- OUTPUT 0 1 0 0 B_WE
135 - - C -- OUTPUT 0 1 0 0 CLK_OUT
141 - - B -- OUTPUT 0 1 0 0 EN
139 - - B -- OUTPUT 0 1 0 0 GDATA0
142 - - B -- OUTPUT 0 1 0 0 GDATA1
148 - - A -- OUTPUT 0 1 0 0 GDATA2
128 - - D -- OUTPUT 0 1 0 0 GDATA3
136 - - C -- OUTPUT 0 1 0 0 LATCH_OUT
140 - - B -- OUTPUT 0 1 0 0 RDATA0
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