/********************************************************************/
/*  Copyright 2004 by SEED Incorporated.							*/
/*  All rights reserved. Property of SEED Incorporated.				*/
/*  Restricted rights to use, duplicate or disclose this code are	*/
/*  granted through contract.									    */
/*  															    */
/********************************************************************/
/* Display parameter definitions based on 625/50 format */
/**********************************************************/
/* ................. */
/* Define frame size */
/* ................. */
/* no of pixels per frame line including horizontal blanking*/
/*定義每行的像素數(shù)，包括消隱行*/
#define VD_FRM_WIDTH 864 
/*定義每幀的行數(shù)，包括消隱行*/
#define VD_FRM_HEIGHT 625 /* total noof lines per frame */
/*定義每幀的大小*/
#define VD_FRM_SIZE (VD_FRM_WIDTH * VD_FRM_HEIGHT)
/* ................... */
/* Horizontal blanking */
/* ................... */
/*行消隱出現(xiàn)的像素位置*/
#define VD_HBLNK_START 720 /* starting location of EAV */
/*行消急結(jié)束的像素位置*/
#define VD_HBLNK_STOP 862 /* starting location of SAV */
/*消隱的像素數(shù)*/
#define VD_HBLNK_SIZE (VD_HBLNK_STOP - VD_HBLNK_START +2/*EAV*/) /* (138) EAV, SAV inclusive */
/* ............................ */
/* Vertical blanking for field1 */
/* ............................ */
/*奇場的場消隱設(shè)置*/
#define VD_VBLNK_XSTART1 720 /* pixel on which VBLNK active */
/* edge occurs for field1 */
#define VD_VBLNK_YSTART1 642 /* line on which VBLNK active */
/* edge occurs for field1 */
#define VD_VBLNK_XSTOP1 720 /* pixel on which VBLNK inactive */
/* edge occurs for field1 */
#define VD_VBLNK_YSTOP1 23 /* line on which VBLNK inactive */
/* edge occurs for field1 */
/* ............................ */
/* Vertical blanking for field2 */
/* ............................ */
/*偶場的場消隱設(shè)置*/
#define VD_VBLNK_XSTART2 360 /* pixel on which VBLNK active */
/* edge occurs for field2 */
#define VD_VBLNK_YSTART2 311 /* line on which VBLNK active */
/* edge occurs for field2 */
#define VD_VBLNK_XSTOP2 360 /* pixel on which VBLNK inactive */
/* edge occurs for field2 */
#define VD_VBLNK_YSTOP2 336 /* line on which VBLNK inactive */
/* edge occurs for field2 */
/* ................................................. */
/* Define vertical blanking bit(VD_VBITn) reg values */
/* ................................................. */
/*第一場重直消隱設(shè)置與清除的所在的行數(shù)*/
/* first line with an EAV with V=1 indicating the start of Field1 vertical blanking */
#define VD_VBIT_SET1 1 
/* first line with an EAV with V=0 indicating the start of Field1 active display*/
#define VD_VBIT_CLR1 23
#define VD_VBLNK1_SIZE (VD_VBIT_CLR1 - VD_VBIT_SET1) /* 19 lines */
/*第二場重直消隱設(shè)置與清除的所在的行數(shù)*/
/* first line with an EAV with V=1 indicating the start of Field2 vertical blanking*/
#define VD_VBIT_SET2 311 
/* first line with an EAV with V=0 indicating the start of Field2 active display*/
#define VD_VBIT_CLR2 336 
#define VD_VBLNK2_SIZE (VD_VBIT_CLR2 - VD_VBIT_SET2) /* 19 lines */
/* ............ */
/* Field timing */
/* ............ */
/* pixel on the first line of Field1 on which FLD ouput is de-asserted*/
#define VD_FIELD1_XSTART 720 
/* line on which FLD is de-asserted */
#define VD_FIELD1_YSTART 1 
/* pixel on the first line of Field1 on which FLD ouput is asserted */
#define VD_FIELD2_XSTART 360
/* line on which FLD is asserted */
#define VD_FIELD2_YSTART 313 
/* .................................... */
/* Define field bit(VD_FBIT) reg values */
/* .................................... */
#define VD_FBIT_CLR 1 /* first line with an EAV with F=0 indicating Field 1 display*/
#define VD_FBIT_SET 313 /* first line with an EAV with F=1 indicating Field 2 display*/

/* ................................ */
/* Define horzontal synchronization */
/* ................................ */
#define VD_HSYNC_START 752
#define VD_HSYNC_STOP 782
/* .......................................... */
/* Define vertical synchronization for field1 */
/* .......................................... */
#define VD_VSYNC_XSTART1 752
#define VD_VSYNC_YSTART1 1
#define VD_VSYNC_XSTOP1 752
#define VD_VSYNC_YSTOP1 3
/* .......................................... */
/* Define vertical synchronization for field2 */
/* .......................................... */
#define VD_VSYNC_XSTART2 320
#define VD_VSYNC_YSTART2 313
#define VD_VSYNC_XSTOP2 320
#define VD_VSYNC_YSTOP2 316
/* ........................................ */
/* Define image offsets for both the fields */
/* which are zero in this example */
/* ........................................ */
#define VD_IMG_HOFF1 0
#define VD_IMG_VOFF1 0
#define VD_IMG_HOFF2 0
#define VD_IMG_VOFF2 0
/* ................................................. */
/* Define image active vertical and horizontal sizes */
/* ................................................. */
#define VD_IMG_HSIZE1 720 /* field1 horizontal image size */
#define VD_IMG_VSIZE1 288 /* field1 vertical image size */
#define VD_IMG_HSIZE2 720 /* field2 horizontal image size */
#define VD_IMG_VSIZE2 288 /* field2 vertical image size */
/* Manipulate field1 and field2 image sizes */
#define VD_IMAGE_SIZE1 (VD_IMG_HSIZE1 * VD_IMG_VSIZE1)
#define VD_IMAGE_SIZE2 (VD_IMG_HSIZE2 * VD_IMG_VSIZE2)
/* Define threshold values in double-words. Both fields should */
/* have same threshold value */
#define VD_VDTHRLD1 (VD_IMG_HSIZE1/8) /* line length in */
#define VD_VDTHRLD2 VD_VDTHRLD1 /* double-words */
/* Define number of events to be generated for field1 and field2 */
#define VD_DISPEVT1 (VD_IMAGE_SIZE1 / (VD_VDTHRLD1 * 8))
#define VD_DISPEVT2 (VD_IMAGE_SIZE2 / (VD_VDTHRLD2 * 8))
#define DISPLAY_FRAME_COUNT 1 /* in this example */
/* ............................................ */
/* EDMA parameters for display Y event that are */
/* specific to this example. */
/* ............................................ */
/* VD_VDTHRLDn is in double-words and 32-bit element size */
#define VD_Y_EDMA_ELECNT (VD_VDTHRLD1 * 2) 
#define VD_Y_EDMA_FRMCNT ((VD_DISPEVT1 + VD_DISPEVT2) * DISPLAY_FRAME_COUNT)
/******************************************************************/
/* Description : 8.bit BT.656 non.continuous frame display */
/* */
/* Some important field descriptions: */
/* */
/* DMODE = 000, 8.bit BT.656 mode */
/* CON = 0 */
/* FRAME = 1, display frame */
/* DF2 = 0 */
/* DF1 = 0, (8.bit non.continuous frame display) */
/* SCALE = 0, no scaling */
/* RESMPL = 0, no resampling */
/* DPK = X, not used in 8.bit display */
/* RSYNC = X, used in Raw mode(Enable second synchronized raw */
/* data channel) */
/* RGBX = X, used in Raw mode(RGB extract enable. Perform */
/* 3/4 FIFO unpacking) */
/* VCTL1S = 00, output HSYNC */
/* VCTL2S = 00, output VSYNC */
/* VCTL3S = 0, output CBLNK */
/* HXS = 0, VCTL1 is an output */
/* VXS = 0, VCTL2 is an output */
/* FXS = 0, VCTL3 is an output */
/* PVPSYN = 0, no previous port synchronization */
/******************************************************************/
#include <vportdis.h>
#include "vportcap.h"
/*................................................................ */
/* global variable declarations */
/* ............................................................... */

//	Uint32 disChaAYSpace  = 0x80000000;
//	Uint32 disChaACbSpace = 0x800675c0; 
//	Uint32 disChaACrSpace = 0x8009b0a0;

	#pragma DATA_SECTION(disChaAYSpace, ".disChaAYSpace") 
	/* buffer to store captured Y-data */
	Uint8 disChaAYSpace[720*588]; 
	#pragma DATA_SECTION(disChaACbSpace, ".disChaACbSpace")
	/* buffer to store captured Cb-data */
	Uint8 disChaACbSpace[360*588]; 
	#pragma DATA_SECTION(disChaACrSpace, ".disChaACrSpace")
	/* buffer to store captured Cr-data */
	Uint8 disChaACrSpace[360*588];
	
	/* handle of vp that to be configured */
	VP_Handle vpDisplayHandle; 
	EDMA_Handle hEdmaVPDispY;
	EDMA_Handle hEdmaVPDispCb;
	EDMA_Handle hEdmaVPDispCr;
	Int32 edmaDispYTccNum = 0; /* EDMA tcc for Y channel */
	Int32 edmaDispCbTccNum = 0; /* EDMA tcc for Cb channel */
	Int32 edmaDispCrTccNum = 0; /* EDMA tcc for Cb channel */
	volatile Uint32 displayFrameCount = 0; /* no of frames that are */
	/* displayed */
	volatile Uint32 dispUnderrun = 0; /* underrun error flag */
	volatile Uint32 disNewFrame =0;
/*................................................................ */
/* Function : bt656_8bit_ncfd */
/* Input(s) : portNumber, video port number i.e. 0, 1 or 2. */
/* Description : Configures given video port for 8.bit BT.656 non. */
/* continuous frame display. */
/*................................................................ */
VP_Handle bt656_8bit_ncfd(int portNumber)
{
	/* Open video port for display ，打開一個視頻口*/
	vpDisplayHandle = VP_open(portNumber, VP_OPEN_RESET);
	if(vpDisplayHandle == INV)
	{
		return (VP_Handle)0xFFFF;
	}
	/*使能視頻口*/
	/* Enable video port functionality in VP Peripheral Control Reg(PCR)*/
	VP_FSETH(vpDisplayHandle , PCR, PEREN, VP_PCR_PEREN_ENABLE);
	/* Set this port to display mode，將此口設(shè)為顯示模式 */
	VP_FSETH(vpDisplayHandle , VPCTL, DISP, VP_VPCTL_DISP_DISPLAY);
	/* ..................... */
	/* Enable all interrupts */
	/* ..................... */
	/*使能相應(yīng)的中斷源*/
	/* enable display complete interrupt */
	VP_FSETH(vpDisplayHandle , VPIE, DCMP, VP_VPIE_DCMP_ENABLE);
	/* enable display underrun interrupt */
	VP_FSETH(vpDisplayHandle , VPIE, DUND, VP_VPIE_DUND_ENABLE);
	/* enable video port global interrupt enable */
	VP_FSETH(vpDisplayHandle , VPIE, VIE, VP_VPIE_VIE_ENABLE);
	/* .................... */
	/* Set all other fields */
	/* .................... */
	/* set frame size ，設(shè)置顯示幀的大小*/
	VP_RSETH(vpDisplayHandle , VDFRMSZ,VP_VDFRMSZ_RMK(VD_FRM_HEIGHT, VD_FRM_WIDTH));
	/*設(shè)置信號VBLNK的時序*/
	/* set horizontal blanking，設(shè)置水平消隱的起始位置與停止位置720～856 */
	VP_RSETH(vpDisplayHandle , VDHBLNK,VP_VDHBLNK_RMK(VD_HBLNK_STOP, 
													  VP_VDHBLNK_HBDLA_NONE,
													  VD_HBLNK_START));
	
	/* set vertical blanking start for field1，設(shè)置第一場的垂直消隱的位置 */
	VP_RSETH(vpDisplayHandle , VDVBLKS1,VP_VDVBLKS1_RMK(VD_VBLNK_YSTART1,
														VD_VBLNK_XSTART1));
	/* set vertical blanking end for field1 */
	VP_RSETH(vpDisplayHandle , VDVBLKE1,VP_VDVBLKE1_RMK(VD_VBLNK_YSTOP1, 
													    VD_VBLNK_XSTOP1));
	/* set vertical blanking start for field2 ，設(shè)置第二場的垂直消隱的位置*/
	VP_RSETH(vpDisplayHandle , VDVBLKS2,VP_VDVBLKS2_RMK(VD_VBLNK_YSTART2, 
													    VD_VBLNK_XSTART2));
	/* set vertical blanking end for field2 */
	VP_RSETH(vpDisplayHandle , VDVBLKE2,VP_VDVBLKE2_RMK(VD_VBLNK_YSTOP2, 
														VD_VBLNK_XSTOP2));
	/*設(shè)置EAV與SAV中的V位的值*/
	/* set vertical blanking bit register for field 1(VD_VBIT1) */
	/*設(shè)置第一場的消隱的行數(shù)*/
	VP_RSETH(vpDisplayHandle , VDVBIT1,VP_VDVBIT1_RMK(VD_VBIT_CLR1, 
											    	  VD_VBIT_SET1));
	/* set vertical blanking bit register for field 2(VD_VBIT2) */
	/*設(shè)置第二場的消隱的行數(shù)*/
	VP_RSETH(vpDisplayHandle , VDVBIT2,VP_VDVBIT2_RMK(VD_VBIT_CLR2, 
													  VD_VBIT_SET2));
	/* No image offsets in this example */
	/* set image size for field1,每一場設(shè)置圖像的大小 */
	VP_RSETH(vpDisplayHandle , VDIMGSZ1,VP_VDIMGSZ1_RMK(VD_IMG_VSIZE1, 
														VD_IMG_HSIZE1));
	/* set image size for field2，設(shè)置第二場圖像的大小 */
	VP_RSETH(vpDisplayHandle , VDIMGSZ2,VP_VDIMGSZ1_RMK(VD_IMG_VSIZE2, 
														VD_IMG_HSIZE2));
	/*設(shè)置FLD信號的邏輯*/
	/* set field1 timing ，設(shè)置第一場的起始點(diǎn)*/