LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mult8_rtl IS
	GENERIC(datawidth:INTEGER:=8);									   --乘數(shù)的數(shù)據(jù)寬度
    PORT (
    	clk 		: IN STD_LOGIC;									   --時鐘
        A			: IN STD_LOGIC_VECTOR (datawidth-1 DOWNTO 0);	   --第一個乘數(shù)
        B			: IN STD_LOGIC_VECTOR (datawidth-1 DOWNTO 0);      --第二個乘數(shù)
        P			: OUT STD_LOGIC_VECTOR (datawidth*2-1 DOWNTO 0);   --乘法器的結(jié)果
        start 		: IN STD_LOGIC;                                    --計算開始信號  
        finished 	: BUFFER STD_LOGIC                                 --計算結(jié)束信號
    );
END mult8_rtl;
ARCHITECTURE rtl OF mult8_rtl IS
	SIGNAL A_sig	:STD_LOGIC_VECTOR (datawidth-1 DOWNTO 0);		   --A移位寄存器中的數(shù)據(jù)
	SIGNAL count 	:INTEGER RANGE 0 TO datawidth+1    :=0;            --主節(jié)拍計數(shù)器
	SIGNAL count2   :INTEGER RANGE 0 TO 2              :=0;            --副節(jié)拍計數(shù)器
	COMPONENT addern8												   --引用加法器
	    GENERIC(datawidth:INTEGER:=8);		
        PORT(
			cin 	: IN STD_LOGIC;		
			a		: IN STD_LOGIC_VECTOR(datawidth-1 downto 0);
			b		: IN STD_LOGIC_VECTOR(datawidth-1 downto 0);
			sum		:OUT STD_LOGIC_VECTOR(datawidth-1 downto 0);
			cout	:OUT STD_LOGIC
		);
    END COMPONENT;
    --加法器加數(shù)輸入a
    SIGNAL adder_a		:STD_LOGIC_VECTOR(datawidth-1 downto 0);	
    --加法器加數(shù)輸入b  
    SIGNAL adder_b		:Std_Logic_Vector(datawidth-1 downto 0);  
    --加法器和輸出sum    
    SIGNAL adder_sum	:STD_LOGIC_VECTOR(datawidth-1 downto 0);
    --加法器進(jìn)位輸入
    SIGNAL adder_cin	:STD_LOGIC;                                   
    --加法器進(jìn)位輸出
    SIGNAL adder_cout	:STD_LOGIC;         
    --一個datawidth寬的全零信號                          
    SIGNAL zero			:STD_LOGIC_VECTOR(datawidth-1 downto 0);      
    --保持乘法結(jié)果的移位寄存器
    SIGNAL P_sig		:STD_LOGIC_VECTOR (datawidth*2-1 DOWNTO 0);   
BEGIN
	c1: addern8
   	PORT MAP(
			cin=>adder_cin,
			a=>adder_a,
			b=>adder_b,
			sum=>adder_sum,
			cout=>adder_cout
	    );
	    
--主進(jìn)程。負(fù)責(zé)乘法結(jié)果的移位和從加法器的和中取數(shù)據(jù)
  	PROCESS(clk)
  	BEGIN
   		IF(clk'event and clk='0') THEN
   			IF(count=0 and count2=0) THEN                           
   			    --起始狀態(tài)清零
  				P_sig(datawidth-1 downto 0)<=zero;
  				P_sig(datawidth*2-1 downto datawidth)<=zero;
   			ELSIF(A_sig(0)='1' and count2=0) THEN					
   			    --做加法運算	
  			ELSIF(A_sig(0)='1' and count2=1) THEN                   
  			    --取和的結(jié)果
  				P_sig(datawidth*2-1 downto datawidth)<=adder_sum;
  			ELSIF(count2=2 and count/=count'high) THEN               
  			    --乘法結(jié)果移位
  				P_sig(datawidth*2-2 downto 0)<=P_sig(datawidth*2-1 downto 1);
  				P_sig(datawidth*2-1)<=adder_cout;
  			END IF;
  		END IF;
  	END PROCESS;
  	
  	--該進(jìn)程控制加法器的輸入
  	PROCESS(clk)
  	BEGIN
  		IF(clk'event and clk='0') THEN
  			IF(A_sig(0)='1') THEN
  			    --相加
	  			adder_a<=P_sig(datawidth*2-1 downto datawidth);
	  			adder_b<=B;
	  			adder_cin<='0';
	    	ELSE
	    		adder_a<=zero;
  				adder_b<=zero;
  				adder_cin<='0';
			END IF;
		END IF;	
	END PROCESS; 	
    
    --該進(jìn)程控制主節(jié)拍計數(shù)器和副節(jié)怕計數(shù)器
	PROCESS(clk)
	BEGIN
		IF(Start='1') and finished='1' THEN
			--在乘法器空閑并時來了開始信號
			--則節(jié)怕計數(shù)器復(fù)位，開始計算乘法，同時輸出乘法器計算未完成信號
			count<=0;
			count2<=0;
			finished<='0';
		ELSIF(clk'event and clk='1') THEN
			IF(count=count'high and count2=count2'high) THEN
			    --計算完成，節(jié)拍計數(shù)器停止
				count<=count;
				count2<=count2;
				--輸出指示乘法器空閑
				finished<='1';
			ELSIF(count2=count2'high) THEN
			    --副節(jié)怕計數(shù)器復(fù)位
				count2<=0;
				count<=count+1;
				finished<='0';
			ELSE	
				count2<=count2+1;
				finished<='0';
			END IF;
		END IF;
	END PROCESS;
	
--控制乘數(shù)A寄存器	
  	PROCESS(clk)
  	BEGIN
   		IF(clk'event and clk='0') THEN 
   			IF count=0 THEN
   				--初始化移位寄存器
  				A_sig<=A;
  			ELSIF(count2=2) THEN
  			    --移位
  				A_sig(datawidth-2 downto 0)<=A_sig(datawidth-1 downto 1);
  				A_sig(datawidth-1)<='0';
  			ELSE
  			    --其他情況保持
  				A_sig<=A_sig;
  			END IF;
  		ELSE
  			A_sig<=A_sig;
  		END IF;
  	END PROCESS;
  	
  --乘法器積輸出進(jìn)程
   PROCESS(finished)
   BEGIN	
	   IF finished='1' THEN
	   		p<=p_sig;
	   END IF;
   END PROCESS;		
  	  		
 --zero:一個datawidth寬的全零信號
 	g1:FOR i IN 0 TO datawidth-1 GENERATE
 		zero(i)<='0';
 	END GENERATE; 
END RTL;