LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE	IEEE.STD_LOGIC_ARITH.ALL;							--算術運算包
ENTITY subber8_useadder IS
PORT(
		cin		: IN	STD_LOGIC;						--進位輸入
        a,b     : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);	--被減數和減數
		s   	: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);	--差
        cout    : OUT   STD_LOGIC);						--借位輸出
END subber8_useadder;
ARCHITECTURE rtl OF subber8_useadder IS					
COMPONENT adder8										--引用8位加法器
PORT(
 	  	cin		: IN	STD_LOGIC;						--進位輸入
        a,b     : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);	--加數
		s   	: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);	--和
        cout    : OUT   STD_LOGIC);						--進位輸出
END COMPONENT;
SIGNAL notcin	:STD_LOGIC;								--輸入進位的非
SIGNAL notb		:STD_LOGIC_VECTOR(7 DOWNTO 0);			--輸入減數的非
SIGNAL adder_cout	:STD_LOGIC;							--加法的輸出進位=減法器輸出進位的非						  
BEGIN
	notb<=not b;
	notcin<=not cin;
	subber_useadder:adder8
		PORT MAP (notcin, a,notb,
		          s,adder_cout);
   cout<=not adder_cout;
END rtl;