?? hardware.asm
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//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
r1 = 0x0000 // 24MHz Fosc
[P_SystemClock]=r1 // Initial System Clock
r1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
[P_TimerA_Ctrl]=r1 // Initial Timer A
//R1 = 0xfd00 // 16K
r1 = 0xfced // 15.625K
[P_TimerA_Data]=r1
r1 = 0x00A8 //
[P_DAC_Ctrl] = r1 //
r1 = 0xffff
[P_INT_Clear] = r1 // Clear interrupt occuiped events
R1 = [R_InterruptStatus] //
r1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
[R_InterruptStatus] = r1 //
[P_INT_Ctrl] = r1 //
RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
r1=0x0020;
[P_SystemClock]=r1
r1 = 0x00A8; //
[P_DAC_Ctrl]= r1
r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
[P_TimerA_Ctrl] = r1;
r1 = 0xfe00; // 24K
[P_TimerA_Data] = r1;
r1 = 0xffff
[P_INT_Clear] = r1 // Clear interrupt occuiped events
r1 = [R_InterruptStatus] //
r1 |= C_FIQ_TMA // Enable Timer A FIQ
[R_InterruptStatus] = r1 //
[P_INT_Ctrl] = r1 //
RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
r1 = 0x0000; // 24MHz, Fcpu=Fosc
[P_SystemClock] = r1; // Initial System Clock
r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
[P_TimerA_Ctrl] = r1 // Initial Timer A
//R1 = 0x0003 // 8K
r1 = 0x0000 // Fosc/2
[P_TimerB_Ctrl] = r1; // Initial Timer B -> 8192
//R1 = 0xFFFF
r1 = 0xFA00 // Any time for ADPCM channel 0,1
[P_TimerB_Data] = r1 // 8K sample rate
r1 = 0xffff
[P_INT_Clear] = r1 // Clear interrupt occuiped events
RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
r1 = 0x0006
[P_DAC_Ctrl] = r1
r1 = 0xFE00
[P_TimerA_Data] = r1 //
r1 = [R_InterruptStatus] //
r1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
[R_InterruptStatus] = r1 //
[P_INT_Ctrl] = r1 //
RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
r1 = 0x00A8
[P_DAC_Ctrl] = r1
r1 = 0xFE00
[P_TimerA_Data] = r1 //
r1 = [R_InterruptStatus] //
r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
[R_InterruptStatus] = r1 //
[P_INT_Ctrl] = r1 //
RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
r1 = 0x00A8
[P_DAC_Ctrl] = r1
r1 = 0xFD9A
[P_TimerA_Data] = r1 //
r1 = [R_InterruptStatus] //
r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
[R_InterruptStatus] = r1 //
[P_INT_Ctrl] = r1 //
RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
r1 = 0x00A8
[P_DAC_Ctrl] = r1
r1 = 0xFD00
[P_TimerA_Data] = r1 //
r1 = [R_InterruptStatus] //
r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
[R_InterruptStatus] = r1 //
[P_INT_Ctrl] = r1 //
RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
r1 = 0x0000; // 24MHz, Fcpu=Fosc
[P_SystemClock] = r1; // Frequency 20MHz
r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
[P_TimerA_Ctrl] = r1;
r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
[P_TimerA_Data] = r1;
r1 = 0x0035; // ADINI should be open (107)
[P_ADC_Ctrl] = r1;
r1 = 0x00A8; // Set the DA Ctrl
[P_DAC_Ctrl] = r1;
r1 = 0xffff;
[P_INT_Clear] = r1; // Clear interrupt occuiped events
r1 = [R_InterruptStatus] //
r1 |= C_FIQ_TMA // Enable Timer A FIQ
[R_InterruptStatus] = r1 //
[P_INT_Ctrl] = r1 //
RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
[P_ADC_Ctrl] = r1; //enable ADC
r1=0xfe00; //24K @ 24.576MHz
[P_TimerA_Data] = r1
RETF
F_SP_SACM_DVR_Play_Init_:
r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
[P_ADC_Ctrl] = r1; // Disable ADC
r1 = 0xfd00; // 16K @ 24.576MHz
[P_TimerA_Data] = r1;
RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
push r1,r2 to [sp]
r1=[P_DAC1]
r1 &= ~0x003f
cmp r1,0x8000
jb L_RU_NormalUp
je L_RU_End
L_RU_DownLoop:
call F_Delay
r2 = 0x0001
[P_Watchdog_Clear] = r2
r1 -= 0x40
[P_DAC1] = r1
cmp r1,0x8000
jne L_RU_DownLoop
L_RD_DownEnd:
jmp L_RU_End
L_RU_NormalUp:
L_RU_Loop:
call F_Delay
r2 = 0x0001
[P_Watchdog_Clear] = r2
r1 += 0x40
[P_DAC1] = r1
cmp r1, 0x8000
jne L_RU_Loop
L_RU_End:
pop r1,r2 from [sp]
retf
.ENDP
//............................................................
_SP_RampDnDAC1: .PROC
F_SP_RampDnDAC1:
push r1,r2 to [sp]
//int off
r1 = [P_DAC1]
r1 &= ~0x003F
jz L_RD_End
L_RD_Loop:
call F_Delay
r2 = 0x0001
[P_Watchdog_Clear] = r2
r1 -= 0x40
[P_DAC1] = r1
jnz L_RD_Loop
L_RD_End:
//int fiq,irq
pop r1,r2 from [sp]
retf
.ENDP
//..............................................................
_SP_RampUpDAC2: .PROC
F_SP_RampUpDAC2:
push r1,r2 to [sp]
r1=[P_DAC2]
r1 &= ~0x003f
cmp r1,0x8000
jb L_RU_NormalUp_
je L_RU_End
L_RU_DownLoop_:
call F_Delay
r2 = 0x0001
[P_Watchdog_Clear] = r2
r1 -= 0x40
[P_DAC2] = r1
cmp r1,0x8000
jne L_RU_DownLoop_
L_RD_DownEnd_:
jmp L_RU_End_
L_RU_NormalUp_:
L_RU_Loop_:
call F_Delay
r2 = 0x0001
[P_Watchdog_Clear] = r2
r1 += 0x40
[P_DAC2] = r1
cmp r1, 0x8000
jne L_RU_Loop_
L_RU_End_:
pop r1,r2 from [sp]
retf
.ENDP
//.............................................................
_SP_RampDnDAC2: .PROC
F_SP_RampDnDAC2:
//int off
push r1,r2 to [sp]
r1 = [P_DAC2]
r1 &= ~0x003F
jz L_RD_End_
L_RD_Loop_:
call F_Delay
r2 = 0x0001
[P_Watchdog_Clear] = r2
r1 -= 0x40
[P_DAC2] = r1
jnz L_RD_Loop_
L_RD_End_:
pop r1,r2 from [sp]
retf
.ENDP
//..................................................................
F_Delay:
push r1 to [sp]
r1 = C_RampDelayTime // Ramp Up/Dn delay per step
L_D_Loop:
r1 -= 1
jnz L_D_Loop
pop r1 from [sp]
RETF
////////////////////////////////////////////////////////////////
// Function: I/O Port A configuration
// void SP_Inti_IOA(int Dir, int Data, int Attrib)
////////////////////////////////////////////////////////////////
_SP_Init_IOA: .PROC
PUSH bp TO [sp]
bp = sp + 1
PUSH r1 TO [sp]
r1 = [bp+3] // Port direction
[P_IOA_Dir] = r1
r1 = [bp+4]
[P_IOA_Data] = r1
r1 = [bp+5]
[P_IOA_Attrib] = r1
POP r1 FROM [sp]
POP bp FROM [sp]
RETF
.ENDP
//////////////////////////////////////////////////////////////////
// Function: I/O Port B configuration
// void SP_Inti_IOB(int Dir, int Data, int Attrib)
//////////////////////////////////////////////////////////////////
_SP_Init_IOB: .PROC
PUSH bp TO [sp]
bp = sp + 1
PUSH r1 TO [sp]
r1 = [bp+3] // Port direction
[P_IOB_Dir] = r1
r1 = [bp+4]
[P_IOB_Data] = r1
r1 = [bp+5]
[P_IOB_Attrib] = r1
POP r1 FROM [sp]
POP bp FROM [sp]
RETF
.ENDP
//////////////////////////////////////////////////////////////////
// Function: Get data from port
// int SP_Import(unsigned int Port)
//////////////////////////////////////////////////////////////////
_SP_Import: .PROC
PUSH bp TO [sp]
bp = sp + 1
r1 = [bp+3] // Port Number
r1 = [r1]
POP bp FROM [sp]
RETF
.ENDP
_SP_Export: .PROC
PUSH bp,bp TO [sp]
sp = sp + 1
PUSH r1,r2 TO [sp]
r1 = [bp+3] // Port Number
r2 = [bp+4] // Value
[r1] = r2
POP r1,r2 FROM [sp]
POP bp,bp FROM [sp]
RETF
.ENDP
//////////////////////////////////////////////////////////////////
// Function: Get data from resource(ROM area)
// int SP_GetResource(int Addr, int Page)
//////////////////////////////////////////////////////////////////
_SP_GetResource: .PROC
push bp to [sp]
bp = sp + 1
r1 = [bp+3] // Address
r2 = [bp+4] // Page
r2 = r2 lsl 4 // Prepare Page for SR
r2 = r2 lsl 4
r2 = r2 lsl 2
sr &= 0x03f // Change Page
r2 |=sr //
sr = r2 //
r1 = D:[r1] // Get data
pop bp from [sp]
retf
.ENDP
//........................................
F_SP_GetResource:
r2 = r2 lsl 4 // Prepare Page for SR
r2 = r2 lsl 4
r2 = r2 lsl 2
sr &= 0x03f // Change Page
r2 |=sr //
sr = r2 //
r1 = D:[r1] // Get data
retf
//////////////////////////////////////////////////////////////////
// Functions: Reserve old defintion
// Note: 1. Some user who use old library may use the old name
// 2. Have to be put at the end of this file
//////////////////////////////////////////////////////////////////
.PUBLIC F_RampUpDAC1
.PUBLIC F_RampDnDAC1
.PUBLIC F_RampUpDAC2
.PUBLIC F_RampDnDAC2
.PUBLIC _STD_RampUpDAC1
.PUBLIC _STD_RampDnDAC1
.PUBLIC _STD_RampUpDAC2
.PUBLIC _STD_RampDnDAC2
.DEFINE F_RampUpDAC1 F_SP_RampUpDAC1
.DEFINE F_RampDnDAC1 F_SP_RampDnDAC1
.DEFINE F_RampUpDAC2 F_SP_RampUpDAC2
.DEFINE F_RampDnDAC2 F_SP_RampDnDAC2
.DEFINE _STD_RampUpDAC1 _SP_RampUpDAC1
.DEFINE _STD_RampDnDAC1 _SP_RampDnDAC1
.DEFINE _STD_RampUpDAC2 _SP_RampUpDAC2
.DEFINE _STD_RampDnDAC2 _SP_RampDnDAC2
///////////////////////////////////////////////////////////////////
//========================================================================================
// End of hardware.asm
//========================================================================================
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