;=========================================================================
ACK_S2:
        TCLR    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as input
        TBIT    *+XAR6[AR0],#SCL_BIT    
        MOVB    *+XAR4[0],#ACK_S3_INDEX,TC       
        EDIS   
        LRETR

;=========================================================================
; Issue Acknowledge
; STATE 3: Drive the SCL to LOW & Release the SDA line
;=========================================================================
ACK_S3
        TSET    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as output
        TCLR    *+XAR6[AR0],#SCL_BIT        ; Drive the SCL pin LOW 

        TCLR    *+XAR5[0],#(SDA_BIT)      ; Set the SDA pin as input  
        MOV     *+XAR4[0],#IDLE_INDEX        
        EDIS   
        LRETR

;======================================================================
;  Data Receive State Machine
;  RSTATE1: Initialize the bit counter
;=====================================================================
RECV_S1:
        MOV     *+XAR4[3],#8            ; bitCntr=8
        MOVB    *XAR4,#RECV_S2_INDEX,UNC
        MOV     *+XAR4[2],#0
        EDIS   
        LRETR     

;======================================================================
;  Data Receive State Machine
;  RSTATE2: De-assert SCL, Shift in SDA if SCL is sampled HIGH
;=====================================================================
RECV_S2:
        TCLR    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as input
        TBIT    *+XAR6[AR0],#SCL_BIT    
        SBF     RECV_S2_EXIT,NTC
        
        MOV     *+XAR4[0],#RECV_S3_INDEX
        TBIT    *+XAR5[AR0],#SDA_BIT         
        MOV     ACC,*+XAR4[2]<<1
        SBF     SDAIN_LO,NTC
        
        OR      ACC,#1

SDAIN_LO:
        MOV     *+XAR4[2],AL        

RECV_S2_EXIT:
        EDIS   
        LRETR

;======================================================================
; Data Receive State Machine       
; RSTATE 3: Drive SCL pin LOW
;=========================================================================
RECV_S3:
        TSET    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as output
        TCLR    *+XAR6[AR0],#SCL_BIT        ; Drive the SCL pin LOW 
        MOV     *+XAR4[0],#RECV_S2_INDEX

        DEC     *+XAR4[3]
        SBF     RECV_S3_EXIT,NEQ

        MOV     *+XAR4[0],#IDLE_INDEX
        AND     *+XAR4[2],#0ffh

RECV_S3_EXIT:
        EDIS   
        LRETR


;======================================================================
;  Data Transmit State Machine
;  TSTATE1: Initialize the bit counter
;=====================================================================
TXMIT_S1:
        MOV     *+XAR4[3],#8                ; bitCntr=8
        MOVB    *XAR4,#TXMIT_S2_INDEX,UNC
        EDIS   
        LRETR     

;======================================================================
;  Data Transmit State Machine
;  TSTATE2: Drive SCL LOW & shiftout data to SDA line
;=====================================================================
TXMIT_S2:
        TSET    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as output
        TCLR    *+XAR6[AR0],#SCL_BIT        ; Drive the SCL pin LOW 
 
        MOV     T,*+XAR4[3]                 ; T=bitCntr

        TBIT    *+XAR4[2],T
        SBF     TX_SDA_HI,TC
            
        MOV    *+XAR4[0],#TXMIT_S3_INDEX 
        TSET    *+XAR5[0],#(SDA_BIT)      ; Set the SDA pin as output
        TCLR    *+XAR5[AR0],#SDA_BIT        ; Drive the SDA pin LOW             
        EDIS   
        LRETR

TX_SDA_HI:
        TCLR    *+XAR5[0],#(SDA_BIT)      ; Set the SDA pin as input
        TBIT    *+XAR5[AR0],#SDA_BIT    
        MOVB    *+XAR4[0],#TXMIT_S3_INDEX,TC        
        EDIS   
        LRETR

;======================================================================
;  Data Transmit State Machine
;  TSTATE3: De-select SCL, and move to next state if sampled HIGH
;=====================================================================
TXMIT_S3:
        TCLR    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as input
        TBIT    *+XAR6[AR0],#SCL_BIT    
        SBF     TXMIT_S3_EXIT,NTC
        
        INC     *+XAR4[3]                   ; bitCntr++
        MOV     *+XAR4[0],#TXMIT_S2_INDEX
        MOV     ACC,*+XAR4[3]
        TCLR    AL,#4
        MOVB    *+XAR4[0],#TXMIT_S4_INDEX,EQ 
                                            ; Go to ack receive after Txmit
TXMIT_S3_EXIT:   
        EDIS   
        LRETR

;======================================================================
;  Data Transmit State Machine
;  TSTATE4: Drive SCL LOW, and De-select SDA
;=====================================================================
TXMIT_S4:
        TSET    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as output
        TCLR    *+XAR6[AR0],#SCL_BIT        ; Drive the SCL pin LOW 
        TCLR    *+XAR5[0],#(SDA_BIT)      ; Set the SDA pin as input
        MOV    *+XAR4[0],#TXMIT_S5_INDEX
        EDIS   
        LRETR

;======================================================================
;  Data Transmit State Machine (Read Acknowledge)
;  TSTATE5: De-Assert SCL, Shift in ACK if SCL sampled HIGH
;=====================================================================
TXMIT_S5:
        TCLR    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as input
        TBIT    *+XAR6[AR0],#SCL_BIT    
        SBF     TXMIT_S5_EXIT,NTC
        
        MOV     *+XAR4[0],#TXMIT_S6_INDEX
        
        TCLR    *+XAR4[1],#ACKSTAT_BIT
        TBIT    *+XAR5[AR0],#SDA_BIT         
        SBF     TXMIT_S5_EXIT,NTC
        TSET    *+XAR4[1],#ACKSTAT_BIT

TXMIT_S5_EXIT:
        EDIS   
        LRETR

;======================================================================
;  Data Transmit State Machine (Read Acknowledge)
;  TSTATE6: Drive SCL LOW
;=====================================================================
TXMIT_S6:
        TSET    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as output
        TCLR    *+XAR6[AR0],#SCL_BIT        ; Drive the SCL pin LOW 
        MOV     *+XAR4[0],#IDLE_INDEX       ; Update the Task to next state  
        EDIS   
        LRETR

;======================================================================
;  IDLE STATE
;=====================================================================
IDLE_S1:
        EDIS   
        LRETR

    .align 2
    
TASK_PTR:
        .xlong IDLE_S1
        .xlong START_S1
        .xlong START_S2
        .xlong START_S3
        .xlong START_S4
    
        .xlong STOP_S1
        .xlong STOP_S2
        .xlong STOP_S3
        
        .xlong RSTART_S1
        .xlong RSTART_S2
        .xlong RSTART_S3

        .xlong ACK_S1
        .xlong ACK_S2
        .xlong ACK_S3

        .xlong RECV_S1
        .xlong RECV_S2
        .xlong RECV_S3

        .xlong TXMIT_S1
        .xlong TXMIT_S2
        .xlong TXMIT_S3
        .xlong TXMIT_S4
        .xlong TXMIT_S5
        .xlong TXMIT_S6