//
//      TMDX ALPHA RELEASE
//      Intended for product evaluation purposes
//
//###########################################################################
//
// FILE:	DSP28_28xSWPrioritizedInterrupts.c
//
// TITLE:	DSP28 Software Prioritized Interrupt Example.
//
// ASSUMPTIONS:
//
//          This program requires the DSP28 header files.  To compile the
//          program as is, it should reside in the DSP28/examples/sw_prioritized_interrupts 
//          sub-directory.
//
//          As supplied, this project is configured for "boot to H0" operation.  
//
// DESCRIPTION:
//
//          For more information on F2810/12 interrupt priorities, refer to the
//          ReadMe_Example_28xISRPriorities.pdf file included with this example.
//
//          This program simulates interrupt conflicts by writing to the
//          PIEIFR registers.  This will simulate multiple interrupts coming into
//          the PIE block at the same time. 
//
//          The interrupt service routine routines are software prioritized
//          by the table found in the DSP28_SWPrioritizedIsrLevels.h file.
//
//          1) Before compiling you must set the Global and Group interrupt priorities
//             in the DSP28_SWPrioritizedIsrLevels.h file.
//
//          2) Compile the code, load, and run
//
//          3) At the end of each test there is a hard coded breakpoint.  When code
//             stops at the breakpoint, examine the ISRTrace buffer to see the order
//             in which the ISR's completed.    All PIE interrupts will add to the
//             ISRTrace.
//
//             The ISRTrace will consist of a list of hex values as shown:
//
//                                  0x00wx    <- PIE Group w interrup x finished first
//                                  0x00yz    <- PIE Group y interrupt z finished next
//
//          4) If desired, set a new set of Global and Group interrupt priorites
//             and repeat the test to see the change.
//          
//
//          Watch Variables:
//                ISRTrace[50]           Trace of ISR's in the order they complete
//                                       After each test, examine this buffer
//                                       to determine if the ISR's completed in
//                                       the order desired. 
//
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  0.57| 06 Jun 2002 | L.H. | First Release
//###########################################################################


// Step 0.  Include required header files
         // DSP28_Device.h: device specific definitions #include statements for
         // all of the peripheral .h definition files.
         // DSP28_Example.h is specific for the given example.  

#include "DSP28_Device.h"

// Define which interrupts are used in the PIE for each group.
#define ISRS_GROUP1  (M_INT1|M_INT2|M_INT4|M_INT5|M_INT6|M_INT7|M_INT8)
#define ISRS_GROUP2  (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT7)
#define ISRS_GROUP3  (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT7)
#define ISRS_GROUP4  (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT7)
#define ISRS_GROUP5  (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT7)
#define ISRS_GROUP6  (M_INT1|M_INT2|M_INT5|M_INT6)
#define ISRS_GROUP9  (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5)


// This array will be used as a trace to check the order that the
// interrupts were serviced
Uint16  ISRTrace[50];
Uint16  ISRTraceIndex;  // used to update an element in the trace buffer

void main(void)
{
   Uint16 i;

// Step 1. Initialize System Control registers, PLL, WatchDog, Clocks to default state:
        // This function is found in the DSP28_SysCtrl.c file.
	InitSysCtrl();

// Step 2. Select GPIO for the device or for the specific application:
        // This function is found in the DSP28_Gpio.c file.
	// InitGpio();  // Skip for this test

// Step 3. Initialize PIE vector table:
	// The PIE vector table is initialized with pointers to shell Interrupt 
        // Service Routines (ISR).  The shell routines are found in DSP28_DefaultIsr.c.
	// Insert user specific ISR code in the appropriate shell ISR routine in 
        // the DSP28_DefaultIsr.c file.

	// Disable and clear all CPU interrupts:
	DINT;
	IER = 0x0000;
	IFR = 0x0000;

	// Initialize Pie Control Registers To Default State:
        // This function is found in the DSP28_PieCtrl.c file.
	InitPieCtrl();

	// Initialize the PIE Vector Table To a Known State:
        // This function is found in DSP28_PieVect.c.
	// This function populates the PIE vector table with pointers
        // to the shell ISR functions found in DSP28_DefaultIsr.c.
	InitPieVectTable();	
	
// Step 4. Initialize all the Device Peripherals to a known state:
	// This function is found in DSP28_InitPeripherals.c
    // InitPeripherals();
   
// Step 5. User specific functions, Reassign vectors (optional), Enable Interrupts:
	
    
// Step 6. Test:	

// CASE 1:
//     Force all group 1 interrupts at once by writing to the PIEIFR1 register

	   // Clear the trace buffer
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;

       // Force all valid interrupts for Group 1
       PieCtrlRegs.PIEIFR1.all = (M_INT1|M_INT2|M_INT4|M_INT5|M_INT6|M_INT7|M_INT8);  

       // Enable PIE group 1 interrupt 1-8 for T1PINT
       PieCtrlRegs.PIEIER1.all = 0x00FF;
	
       // Enable CPU INT1
       IER |= M_INT1;

       // Enable global Interrupts:
	   EINT;   // Enable Global interrupt INTM
	   
	   // Wait for all Group 1 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR1.all != 0x0000 ){}
	   
       // Stop here and check the ISRTrace to determine which order the 
       // ISR Routines completed.  The order is dependant on the priority
       // assigned in the DSP28_SWPrioritizedIsrLevels.h file
       // 
       // The ISRTrace will contain a list of values corresponding to the
       // interrupts serviced in the order they were serviced. 
	   // For example if the ISRTrace looks like this
	   //        0x0014     ISR Group 1 interrupt 4
	   //        0x0017     ISR Group 1 interrupt 7
	   //        0x0016     ISR Group 1 interrupt 6
	   //        0x0000     end of trace
	   asm("        ESTOP0");	

// CASE 2:
//     Force all group 2 interrupts at once by writing to the PIEIFR2 register

	   // Clear the trace buffer
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;

       // Disable Global interrupts
       DINT;
       
       // Clear CPU enable register
       IER &= 0x0000;
       
       // Disable PIE group 2 interrupts 1-8 
       PieCtrlRegs.PIEIER2.all = 0x00FF;

       // Force all valid interrupts for Group 1 and from Group 2
       PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;  

       // Enable PIE group 2 interrupts 1-8 
       PieCtrlRegs.PIEIER2.all = 0x00FF;

       // Enable CPU INT2
       IER |= (M_INT2);

	   // Enable Global interrupts
	   EINT;
	   
	   // Wait for all group 2 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR2.all != 0x0000 ){}
	   
       // Stop here and check the order the ISR's were serviced in the
       // ISRTrace
	   asm("        ESTOP0");
	   
	   
// CASE 3:
//     Force all group 3 interrupts at once by writing to the PIEIFR3 register

	   // Clear the trace buffer
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;

       // Disable Global interrupts
       DINT;

       // Clear CPU enable register
       IER &= 0x0000;
              
       // Disable PIE group 3 interrupts 1-8 
       PieCtrlRegs.PIEIER3.all = 0x00FF;

       // Force all valid interrupts for Group 1 and from Group 2
       PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3;  

       // Enable PIE group 3 interrupts 1-8 
       PieCtrlRegs.PIEIER3.all = 0x00FF;

       // Enable CPU INT3
       IER |= (M_INT3);

	   // Enable Global interrupts
	   EINT;
	   
	   // Wait for all group 3 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR3.all != 0x0000 ){}
	   
       // Stop here and check the order the ISR's were serviced in the
       // ISRTrace
	   asm("        ESTOP0");	   	   	   
	   
// CASE 4:
//     Force all group 4 interrupts at once by writing to the PIEIFR4 register

	   // Clear the trace buffer
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;

       // Disable Global interrupts
       DINT;
       
       // Clear CPU enable register
       IER &= 0x0000;
       
       // Disable PIE group 4 interrupts 1-8 
       PieCtrlRegs.PIEIER4.all = 0x00FF;

       // Force all valid interrupts for Group 4
       PieCtrlRegs.PIEIFR4.all = ISRS_GROUP4;  

       // Enable PIE group 4 interrupts 1-8 
       PieCtrlRegs.PIEIER4.all = 0x00FF;

       // Enable CPU INT4
       IER |= (M_INT4);

	   // Enable Global interrupts
	   EINT;