// Wait for all group 4 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR4.all != 0x0000 ){}
	   
       // Stop here and check the order the ISR's were serviced in the
       // ISRTrace
	   asm("        ESTOP0");	
	   
// CASE 5:
//     Force all group 5 interrupts at once by writing to the PIEIFR5 register

	   // Clear the trace buffer
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;

       // Disable Global interrupts
       DINT;

       // Clear CPU enable register
       IER &= 0x0000;
              
       // Disable PIE group 5 interrupts 1-8 
       PieCtrlRegs.PIEIER5.all = 0x00FF;

       // Force all valid interrupts for Group 5
       PieCtrlRegs.PIEIFR5.all = ISRS_GROUP5;  

       // Enable PIE group 5 interrupts 1-8 
       PieCtrlRegs.PIEIER5.all = 0x00FF;

       // Enable CPU INT5
       IER |= (M_INT5);

	   // Enable Global interrupts
	   EINT;
	   
	   // Wait for all group 5 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR5.all != 0x0000 ){}
	   
       // Stop here and check the order the ISR's were serviced in the
       // ISRTrace
	   asm("        ESTOP0");
	   
// CASE 6:
//     Force all group 6 interrupts at once by writing to the PIEIFR6 register

	   // Clear the trace buffer
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;

       // Disable Global interrupts
       DINT;

       // Clear CPU enable register
       IER &= 0x0000;
              
       // Disable PIE group 6 interrupts 1-8 
       PieCtrlRegs.PIEIER6.all = 0x00FF;

       // Force all valid interrupts for Group 6
       PieCtrlRegs.PIEIFR6.all = ISRS_GROUP6;  

       // Enable PIE group 6 interrupts 1-8 
       PieCtrlRegs.PIEIER6.all = 0x00FF;

       // Enable CPU INT6
       IER |= (M_INT6);

	   // Enable Global interrupts
	   EINT;
	   
	   // Wait for all group 6 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR6.all != 0x0000 ){}
	   
       // Stop here and check the order the ISR's were serviced in the
       // ISRTrace
	   asm("        ESTOP0");

// CASE 8:
//     Force all group 9 interrupts at once by writing to the PIEIFR4 register

	   // Clear the trace buffer
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;

       // Disable Global interrupts
       DINT;
       
       // Clear CPU enable register
       IER &= 0x0000;       
       
       // Disable PIE group 9 interrupts 1-8 
       PieCtrlRegs.PIEIER9.all = 0x00FF;

       // Force all valid interrupts for Group 9
       PieCtrlRegs.PIEIFR9.all = ISRS_GROUP9;  

       // Enable PIE group 9 interrupts 1-8 
       PieCtrlRegs.PIEIER9.all = 0x00FF;

       // Enable CPU INT9
       IER |= (M_INT9);

	   // Enable Global interrupts
	   EINT;
	   
	   // Wait for all group 9 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR9.all != 0x0000 ){}
	   
       // Stop here and check the order the ISR's were serviced in the
       // ISRTrace
	   asm("        ESTOP0");	
	   	
// CASE 9:
//     Force all group 1 and group 2 interrupts at once

       // Setup next test - fire interrupts from Group 1 and Group 2

	   // Clear the trace buffer
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;

       // Disable Global interrupts
       DINT;
       
       // Disable PIE group 1 & group 2 interrupts 1-8 
       PieCtrlRegs.PIEIER1.all = 0x00FF;
       PieCtrlRegs.PIEIER2.all = 0x00FF;

       // Force all valid interrupts for Group 1 and from Group 2
       PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;  
       PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;  

       // Enable PIE group 1 and group 2 interrupts 1-8 
       PieCtrlRegs.PIEIER1.all = 0x00FF;
       PieCtrlRegs.PIEIER2.all = 0x00FF;

       // Enable CPU INT1 and INT2
       IER |= (M_INT1|M_INT2);

	   // Enable Global interrupts
	   EINT;
	   
	   // Wait for all group 1 and group 2 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR1.all != 0x0000 
	      || PieCtrlRegs.PIEIFR2.all != 0x0000 ){}
	   
	   // Check the ISRTrace to determine which order the ISR Routines completed
	   asm("        ESTOP0");	   


// CASE 10:
//     Force all group 1 and group 2 and group 3 interrupts at once

	   // Clear the trace buffer
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;

       // Disable Global interrupts
       DINT;
       
       // Disable PIE group 1 & group 2 interrupts 1-8 
       PieCtrlRegs.PIEIER1.all = 0x00FF;
       PieCtrlRegs.PIEIER2.all = 0x00FF;
       PieCtrlRegs.PIEIER3.all = 0x00FF;

       // Force all valid interrupts for Group1, 2 and 3
       PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;  
       PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;  
       PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3;  

       // Enable PIE group 1, 2 and 3 interrupts 1-8 
       PieCtrlRegs.PIEIER1.all = 0x00FF;
       PieCtrlRegs.PIEIER2.all = 0x00FF;
       PieCtrlRegs.PIEIER3.all = 0x00FF;

       // Enable CPU INT1 and INT2
       IER |= (M_INT1|M_INT2|M_INT3);

	   // Enable Global interrupts
	   EINT;
	   
	   // Wait for all group 1 and group 2 and group 3 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR1.all != 0x0000 
	      || PieCtrlRegs.PIEIFR2.all != 0x0000 
	      || PieCtrlRegs.PIEIFR3.all != 0x0000 ) {}
	      
	   // Check the ISRTrace to determine which order the ISR Routines completed
	   asm("        ESTOP0");	


// CASE 11:
//     Force all used PIE interrupts at once

	   // Clear the trace buffer
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;

       // Disable Global interrupts
       DINT;
       
       // Disable PIE group 1 & group 2 interrupts 1-8 
       PieCtrlRegs.PIEIER1.all = 0x00FF;
       PieCtrlRegs.PIEIER2.all = 0x00FF;
       PieCtrlRegs.PIEIER3.all = 0x00FF;
       PieCtrlRegs.PIEIER4.all = 0x00FF;
       PieCtrlRegs.PIEIER5.all = 0x00FF;
       PieCtrlRegs.PIEIER6.all = 0x00FF;
       PieCtrlRegs.PIEIER9.all = 0x00FF;

       // Force all valid interrupts for all PIE groups
       PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;  
       PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;  
       PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3;  
       PieCtrlRegs.PIEIFR4.all = ISRS_GROUP4;  
       PieCtrlRegs.PIEIFR5.all = ISRS_GROUP5;  
       PieCtrlRegs.PIEIFR6.all = ISRS_GROUP6;  
       PieCtrlRegs.PIEIFR9.all = ISRS_GROUP9;  

       // Enable all PIE group iterrupts 1-8 
       PieCtrlRegs.PIEIER1.all = 0x00FF;
       PieCtrlRegs.PIEIER2.all = 0x00FF;
       PieCtrlRegs.PIEIER3.all = 0x00FF;
       PieCtrlRegs.PIEIER4.all = 0x00FF;
       PieCtrlRegs.PIEIER5.all = 0x00FF;
       PieCtrlRegs.PIEIER6.all = 0x00FF;
       PieCtrlRegs.PIEIER9.all = 0x00FF;

       // Enable CPU INT1 and INT2
       IER |= (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT9);

	   // Enable Global interrupts
	   EINT;
	   
	   // Wait for all group interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR1.all != 0x0000 
	      || PieCtrlRegs.PIEIFR2.all != 0x0000 
	      || PieCtrlRegs.PIEIFR3.all != 0x0000 
          || PieCtrlRegs.PIEIFR4.all != 0x0000 
	      || PieCtrlRegs.PIEIFR5.all != 0x0000 
	      || PieCtrlRegs.PIEIFR6.all != 0x0000 
	      || PieCtrlRegs.PIEIFR9.all != 0x0000 ) {}
	      
	   // Check the ISRTrace to determine which order the ISR Routines completed
	   asm("        ESTOP0");	

} 	



// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here:	
	// If local ISRs are used, reassign vector addresses in vector table as
    // shown in   Step 5

// For this example the ISR routines are in Example_28xSWPrioritizedDefaultIsr.c

//===========================================================================
// No more.
//===========================================================================