module dprams (IOD,B0WA,B0RA,WA,RA,NBWR,NBRD,B0D,B1D,B2D,CLKRAM);

input  [15:0] IOD;
input  [8:0] B0WA,B0RA,WA,RA;
input  [2:0] NBWR,NBRD;
input  CLKRAM;
output  [15:0] B0D, B1D, B2D;

wire  [15:0] IOD,B0D, B1D, B2D;
wire  [8:0] B0WA,B0RA,WA,RA;
wire  [2:0] NBWR,NBRD;
wire  NBWR0,NBRD0,NBWR1,NBRD1,NBWR2,NBRD2;
wire  CLKRAM;

//B0RAM U1 (IOD,wren,B0WA,B0RA,NBWR0,NBRD0,B0D);
//B0RAM U1 (IOD,NBWR0,B0WA,B0RA,NBRD0,CLKRAM,B0D);
B0RAM U1 (CLKRAM,IOD,B0RA,NBRD0,B0WA,NBWR0,B0D);

//B1RAM U2 (IOD,wren,WA,RA,NBWR1,NBRD1,B1D);
//B1RAM U2 (IOD,NBWR1,WA,RA,NBRD1,CLKRAM,B1D);
B1RAM U2 (CLKRAM,IOD,RA,NBRD1,WA,NBWR1,B1D);

//B2RAM U3 (IOD,wren,WA,RA,NBWR2,NBRD2,B2D);
//B2RAM U3 (IOD,NBWR2,WA,RA,NBRD2,CLKRAM,B2D);
B2RAM U3 (CLKRAM,IOD,RA,NBRD2,WA,NBWR2,B2D);
	
//initial 
//  begin
//   wren=1;
//  end
//   assign wren=1'b1;
   assign NBWR0=~NBWR[0];
   assign NBWR1=~NBWR[1];
   assign NBWR2=~NBWR[2];
   assign NBRD0=~NBRD[0];
   assign NBRD1=~NBRD[1];
   assign NBRD2=~NBRD[2];

endmodule