//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //// Clock Generator// Copyright Mentor Graphics Corporation and Licensors 1998.// V1.000// m3s033ct// M320C50 Serial Port Clock Generator.// Provides TX and Rx clocks for the transmitter and receiver.// NTxClock and NRxClock are the inverted TxClock and RxClock respectively.module m3s033ct (Clock, CLKXI, CLKR, NCLKXE, SPC1, RxClockDis,//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //    TCLKX, TxClock, NTxClock, RxClock, NRxClock);    input    Clock, CLKXI, CLKR, NCLKXE, SPC1, RxClockDis;    output   TCLKX, TxClock, NTxClock, RxClock, NRxClock;    reg   TCLKX, TxClock, NTxClock, RxClock, NRxClock;    reg   Clock2, Clock4;// CPU clock divide by 4always @(negedge Clock)begin  if (~NCLKXE) begin    Clock2 <= ~Clock2;    if (Clock2) Clock4 <= ~Clock4;  end  else begin    Clock2 <= 1;    Clock4 <= 1;  endend// Transmit clockalways @(CLKXI or Clock4)begin  TCLKX = Clock4;  TxClock = CLKXI;  NTxClock = ~CLKXI;end// Receive clock.always @(SPC1 or CLKR or TxClock or RxClockDis)begin  if (SPC1) RxClock = TxClock | RxClockDis;  else RxClock = CLKR | RxClockDis;  NRxClock = ~RxClock;endendmodule