//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //// 4-bit Slice Carry Generate// Copyright Mentor Graphics Corporation and Licensors 1998. // V1.100// m3s075ct.v// M320C50 4-bit Slice Carry Generate// Generates the carrys for the 4-bit slices of the ALU// arithmetic unit.module m3s075ct (NG, NP, NC_IN, NC_S);//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //  input [7:0] NG, NP; // input propagate generate signals  input NC_IN; // inverse of carry into ALU    output [7:0] NC_S; // slice carry outputs (low true)  reg [7:0] NC_S;// note these are all defined as parallel although unless you specify tight// timing constraints for this block the synthesiser will throw it all awayalways @(NG or NP or NC_IN)begin  NC_S[0] = !(!(NC_IN & NG[0]) &              !(NG[0] & NP[0]));  NC_S[1] = !(!(NC_IN & NG[0] & NG[1]) &              !(NG[0] & NG[1] & NP[0]) & 	      !(NG[1] & NP[1]));  NC_S[2] = !(!(NC_IN & NG[0] & NG[1] & NG[2]) &              !(NG[0] & NG[1] & NG[2] & NP[0]) & 	      !(NG[1] & NG[2] & NP[1]) &	      !(NG[2] & NP[2]));  NC_S[3] = !(!(NC_IN & NG[0] & NG[1] & NG[2] & NG[3]) &              !(NG[0] & NG[1] & NG[2] & NG[3] & NP[0]) & 	      !(NG[1] & NG[2] & NG[3] & NP[1]) &	      !(NG[2] & NG[3] & NP[2]) &	      !(NG[3] & NP[3]));  NC_S[4] = !(!(NC_IN & NG[0] & NG[1] & NG[2] & NG[3] & NG[4]) &              !(NG[0] & NG[1] & NG[2] & NG[3] & NG[4] & NP[0]) & 	      !(NG[1] & NG[2] & NG[3] & NG[4] & NP[1]) &	      !(NG[2] & NG[3] & NG[4] & NP[2]) &	      !(NG[3] & NG[4] & NP[3]) &	      !(NG[4] & NP[4]));  NC_S[5] = !(!(NC_IN & NG[0] & NG[1] & NG[2] & NG[3] & NG[4] & NG[5]) &              !(NG[0] & NG[1] & NG[2] & NG[3] & NG[4] & NG[5] & NP[0]) & 	      !(NG[1] & NG[2] & NG[3] & NG[4] & NG[5] & NP[1]) &	      !(NG[2] & NG[3] & NG[4] & NG[5] & NP[2]) &	      !(NG[3] & NG[4] & NG[5] & NP[3]) &	      !(NG[4] & NG[5] & NP[4]) &	      !(NG[5] & NP[5]));  NC_S[6] = !(!(NC_IN & NG[0] & NG[1] & NG[2] & NG[3] & NG[4] & NG[5] & NG[6]) &              !(NG[0] & NG[1] & NG[2] & NG[3] & NG[4] & NG[5] & NG[6] & NP[0]) & 	      !(NG[1] & NG[2] & NG[3] & NG[4] & NG[5] & NG[6] & NP[1]) &	      !(NG[2] & NG[3] & NG[4] & NG[5] & NG[6] & NP[2]) &	      !(NG[3] & NG[4] & NG[5] & NG[6] & NP[3]) &	      !(NG[4] & NG[5] & NG[6] & NP[4]) &	      !(NG[5] & NG[6] & NP[5]) &	      !(NG[6] & NP[6]));  NC_S[7] = !(!(NC_S[6] & NG[7]) & !(NG[7] & NP[7]));end  endmodule