//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //// CPU Core// Copyright Mentor Graphics Corporation and Licensors 1998.// V1.203// Revision history// V1.203 - 16 December 1996//          IFnEx signal added.// V1.202 - 2 December 1996//          DFCAuxStall signal added.// V1.201 - 19 November 1996//          Internal memory connection signals revised.// V1.2   - 3 June 1996//          SetBRAF signal added, from m3s003ct.// V1.106 - 10 May 1996// m3s001ct// M320C50 CPU core.// Instantiates://    Pipeline/Decoder//    Program Address Generator, with stack//    Data Address Generator, with auxillary registers and ARAU//    Memory Device Controllers//    Memory Mapped Register decode block//    Parallel Logic Unit//`include "m320c50.inc"module m3s001ct (FClock, Clock, ClockInt, Reset, MPNMC, NBIO, NMIEdge, Intr,//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //    DI, PD, B0D, B1D, B2D, SD, ERdy, PRdy, SRdy,    ExtAccEnab, MemAccEnab, DMAMode, MemCycle,    AI, RNWI, NSTRBI,    B0WA, B0RA, WA, RA, PA, SARA, SAWA, SAPA, NBWR, NBRD, NPCE, NPOE, NPWE,    SRNW, SPND, NSCE, NSWE, NSOE, OA, NPS, NDS, NIS, NWR, NRD,    IOD, OD, NDEN, NBR,    PMMRWrAddr, PMMRRdAddr, PMMRWriteData, PMMRRdData, PMMRWr, PMMRRd,    XF, HM, InsFetch,    iIdle, iIdle2, NIACK, RNWO, NSTRBO, Wakeup,    DWAccess, DRAccess, PAccess, IWAccess, IRAccess,    DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo, PAddr);    input         FClock, Clock, ClockInt, Reset, MPNMC;    input  [15:0] DI, PD, B0D, B1D, B2D, SD;    input         ERdy, PRdy, SRdy, ExtAccEnab, MemAccEnab, DMAMode;    input         NBIO, NMIEdge, RNWI, NSTRBI;    input  [14:0] AI;    input  [15:0] Intr, PMMRRdData;    output [14:0] PA, SARA, SAWA, SAPA;    output [8:0]  B0WA, B0RA, WA, RA;    output [2:0]  NBWR, NBRD;    output        NPCE, NPOE, NPWE;    output [6:0]  PMMRWrAddr, PMMRRdAddr;    output [15:0] OA, IOD, OD, PMMRWriteData;    output [`C_NOSB-1:0] SRNW, SPND, NSCE, NSWE, NSOE;    output        NPS, NDS, NIS, NWR, NRD, NDEN, PMMRWr, PMMRRd, MemCycle;    output        XF, HM, NBR, InsFetch, iIdle, iIdle2, NIACK, Wakeup;    output        RNWO, NSTRBO, DWAccess, DRAccess, PAccess, IWAccess, IRAccess;    output  [2:0] DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo;    output  [1:0] PAddr;    wire [14:0] PA, SARA, SAWA, SAPA, iSARA, iSAWA;    wire [15:0] OA;    wire [8:0]  B0WA, B0RA, WA, RA;    wire [2:0]  NBWR, NBRD;    wire        NPCE, NPOE, NPWE;    wire        NDS, NPS, NIS, NWR, NRD, NDEN, NBR;    wire        iNDEN;    wire [15:0] DataWrite;    wire [`C_NOSB-1:0] SRNW, SPND, NSCE, iSRNW, iSPND;    wire [`C_NOSB-1:0] NSWE, NSOE, iNSCE, iNSWE, iNSOE;    wire        InsFetch, iIdle, iIdle2, NIACK, RNWO, NSTRBO, Wakeup;    tri  [15:0] ProgRead, DataRead;    wire        RAM, OVLY, TRM, CNF, XF, HM, BRAF, NDX;    wire  [4:0] IntPtr;    wire [15:0] ProgBus, DataBus;    wire [15:0] ProgAddr, WriteAddr, ReadAddr;    wire [14:0] SpAddr;    wire        MMRReady;    wire [18:0] PACntrl;    wire [33:0] DACntrl;    wire [1:0]  LdCntrl;    wire [6:0]  PLUCntrl;    wire [6:0]  RdAddr, WrAddr, PMMRWrAddr, PMMRRdAddr;    wire [7:0]  ARImm;    wire        AdvPipe, InsCycle, AdvCycle, PrmRdy;    wire        MemCycle, MemCycle1, MemCycle2, MemCycle3, MemCycle4;    wire        SpPmRdy, SpDmRdy, ExPmRdy, ExDmRdy;    wire        MMWrRq, MMRdRq, WriteReady, ContextSave, ContextRestore;    wire        DpDataValid, SpDataValid, ExDataValid, MMDataValid, ProgValid;    wire        PrDpReq, PrSpReq, PrPrReq, PrExReq;    wire        PwDpReq, PwSpReq, PwPrReq, PwExReq;    wire [2:0]  DpWrReq, DpRdReq;    wire        SpWrReq, SpRdReq, ExWrReq, ExRdReq, IOWrReq, IORdReq;    wire [3:0]  IntRegCntrl;    wire [1:0]  RptRegCntrl;    wire [5:0]  BrptRegCntrl;    wire [15:0] AuxRegCntrl;    wire [5:0]  TRegCntrl;    wire [7:0]  GAddrEnab;    wire [1:0]  BMARRegCntrl;    wire [14:0] CALURegCntrl;    wire [9:0]  CALUSelCntrl;    wire [11:0] ALUCntrl;    wire [6:0]  SRCntrl;    wire [8:0]  SetClrCntrl;    wire        AVIS, SpDaRdWrDet, SpPrRdWrDet, DpRdWrDet;    wire        MultCntrl, ClrOV, BitTestEnab, SetBRAF, ClrBRAF, LdARTC;    wire        PLUZero, ARZ, ARTC, PLUCmpr, iTBLW, LdPortAddr, iMMR, RptOut;    wire        AccNZ, AccLZ, TC, OV, C, NormEnab, PMMRWr, PMMRRd;    wire [15:0] IOD, OD, Intr, PMMRWriteData, PMMRRdData;    wire  [4:0] IntVect;    wire        INTM, IntReq, IntrStuff, IFnEx, IntrEx, ClrIntm, SetIntm;    wire        PrWrRdy, SpWrRdy, ExWrRdy, ODRegEnab;    wire        DWAccess, DRAccess, PAccess, IWAccess, IRAccess;    wire  [2:0] DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo;    wire  [1:0] PAddr;// Address bits for wait-state generatorassign DWAddrHi = WriteAddr[15:13];assign DWAddrLo = WriteAddr[3:1];assign DRAddrHi = ReadAddr[15:13];assign DRAddrLo = ReadAddr[3:1];assign PAddr = ProgAddr[15:14];// MemCycleassign MemCycle1 = MemCycle;assign MemCycle2 = MemCycle;assign MemCycle3 = MemCycle;assign MemCycle4 = MemCycle;// Pipeline controllerm3s002ct U1 (ProgRead, DataRead, Clock, Reset, ContextSave, ContextRestore,    SpPmRdy, PrmRdy, ExPmRdy, SpDmRdy, ExDmRdy, MMRReady, DMAMode,    DpDataValid, SpDataValid, ExDataValid, MMDataValid, ProgValid,    ARZ, NBIO, TC, AccNZ, AccLZ, OV, C, NormEnab, ClrOV, BitTestEnab,    ProgBus, DataBus, RptRegCntrl,    INTM, IntReq, IntVect, IntrStuff, IFnEx, IntrEx, ClrIntm, SetIntm,    PACntrl, DACntrl, LdCntrl, PLUCntrl[4:0], MultCntrl, LdARTC,    CALURegCntrl, CALUSelCntrl, ALUCntrl, SRCntrl, SetClrCntrl, PLUCmpr,    iTBLW, LdPortAddr, iMMR, RptOut, iIdle, iIdle2,    RdAddr, WrAddr, ARImm, DFCAuxStall,    AdvPipe, InsCycle, AdvCycle, MemCycle, DataWrite, NIACK);// Program address generatorm3s003ct U2 (ProgBus, DataBus, IntPtr, WrAddr[4:0], B0D, PD, DI,    Clock, MemCycle1, InsCycle, Reset, PACntrl, BMARRegCntrl, BrptRegCntrl, iMMR,    uPMode, CNF, RAM, BRAF, IFnEx, SetBRAF, ClrBRAF, iTBLW, DMAMode,    PrProgValid, DpProgValid, SpProgValid, ExProgValid,    SpPrRdWrDet,    ProgAddr, DataWrite, PrDpReq, PrSpReq, PrPrReq, PrExReq,    PwDpReq, PwSpReq, PwPrReq, PwExReq, ProgValid,    DataRead, InsFetch, ProgRead);// Data address generatorm3s005ct U3 (DataBus, ProgBus, RdAddr, WrAddr, ARImm, LdPortAddr,    B0D, B1D, B2D, SD, DI,    DACntrl, LdCntrl, AuxRegCntrl, CALUSelCntrl[8:6],    Clock, Reset, AdvCycle, MemCycle2, MemCycle3, OVLY, CNF,    ContextSave, ContextRestore, iMMR, NDX, DMAMode, DFCAuxStall,    MMWrRq, MMRdRq, PrWrRdy, SpWrRdy, ExWrRdy, SpDaRdWrDet, DpRdWrDet,    DpWrReq, SpWrReq, ExWrReq, IOWrReq, DpRdReq, SpRdReq, ExRdReq, IORdReq,    WriteAddr, ReadAddr, WriteReady, ARZ, ARTC, DataWrite, DataRead);// Program memory controllerm3s013ct U4 (ProgAddr[14:0], PrPrReq, PwPrReq, PRdy,    MemCycle, FClock, Clock, Reset, MemAccEnab, PACntrl[14],    PA, NPCE, NPOE, NPWE, WriteReady,    PrmRdy, PrWrRdy, PrProgValid);// Single-port memory controllerm3s012ct U5 (ProgAddr[14:0], WriteAddr[14:0], ReadAddr[14:0],     PrSpReq, PwSpReq, SpWrReq, SpRdReq, SRdy,    MemCycle, FClock, Clock, Reset, MemAccEnab, PACntrl[14],    iSARA, iSAWA, SAPA, iSRNW, iSPND, iNSCE, iNSWE, iNSOE,    WriteReady, SpPmRdy, SpDmRdy,    SpDataValid, SpProgValid, SpWrRdy, SpDaRdWrDet, SpPrRdWrDet);// Dual-port memory controllerm3s011ct U6 (ProgAddr[8:0],    {WriteAddr[9],WriteAddr[7:0]}, {ReadAddr[9],ReadAddr[7:0]}, CNF,    PwDpReq, PrDpReq, DpWrReq, DpRdReq, MemCycle, FClock, Clock, Reset,    MemAccEnab, PACntrl[14], WriteReady,    B0WA, B0RA, WA, RA, NBWR, NBRD, DpDataValid, DpProgValid, DpRdWrDet);// External memory controllerm3s014ct U7 (ProgAddr, WriteAddr, ReadAddr,     PrExReq, PwExReq, ExWrReq, ExRdReq, IOWrReq, IORdReq, ERdy, WriteReady,    MemCycle, FClock, Clock, Reset, GAddrEnab, ExtAccEnab, MemAccEnab, AVIS,    PACntrl[14], PACntrl[8],    OA, NDS, NPS, NIS, NWR, NRD, ExPmRdy, ExDmRdy, ExWrRdy,    ExDataValid, ExProgValid, iNDEN, NBR, ODRegEnab, RNWO, NSTRBO,    DWAccess, DRAccess, PAccess, IWAccess, IRAccess);// Memory-mapped register decoderm3s015ct U8 (DataBus, WriteAddr[6:0], ReadAddr[6:0],    FClock, Clock, Reset, AdvPipe, MemCycle,    MPNMC, MMWrRq, MMRdRq, ContextSave, ContextRestore,    SetBRAF, ClrBRAF, iMMR, RptOut, PMMRRdData,    uPMode, RAM, OVLY, IntPtr, TRM, BRAF, NDX, AVIS, GAddrEnab,    IntRegCntrl, RptRegCntrl, BrptRegCntrl, PLUCntrl[6:5], AuxRegCntrl, TRegCntrl,    BMARRegCntrl, MMDataValid, MMRReady, PMMRWr, PMMRRd, WriteReady,    PMMRWrAddr, PMMRRdAddr, PMMRWriteData, DataWrite, DataRead);// Parallel logic unitm3s010ct U9 (ProgBus, DataBus, PLUCntrl, Clock, Reset, iMMR, DMAMode,    DataWrite, DataRead, PLUZero);// CALUm3s007ct U10 (ProgBus, DataBus, Clock, MemCycle4, Reset,    TRM, TRegCntrl, CALURegCntrl, CALUSelCntrl, ALUCntrl, SRCntrl,    SetClrCntrl[7:0], ContextSave, ContextRestore, LdARTC, ARTC,    PLUCmpr, PLUZero, MultCntrl, ClrOV, BitTestEnab, iMMR, DMAMode,    AccNZ, AccLZ, TC, OV, C, NormEnab, CNF, XF, HM, DataWrite, DataRead);// Interrupt Controllerm3s060ct U11 (DataBus, IntRegCntrl, DACntrl[13],    SetClrCntrl[8], SetClrCntrl[0], iMMR, MemAccEnab,    Clock, ClockInt, Reset, MemCycle,    IntrStuff, IntrEx, NMIEdge, Intr, ClrIntm, SetIntm,    INTM, IntReq, IntVect, Wakeup, DataWrite, DataRead);// External DMA controllerm3s019ct U12 (Clock, DMAMode, ODRegEnab, RNWI, NSTRBI, AI, DI,    SD, iSAWA, iSARA, iNSCE, iSPND, iSRNW, iNSWE, iNSOE, iNDEN,    DataWrite, IOD, OD, SAWA, SARA, NSCE, SPND, SRNW, NSWE, NSOE, NDEN);endmodule