//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //// M320C50 DSP// Copyright Mentor Graphics Corporation and Licensors 1998.// V1.211// Revision history// V1.211 - 19 November 1996//          Internal memory connection signals revised.// m3s000ct// M320C50 Digital Signal Processor.// Instantiates://    CPU Core//    Peripheral Block//    Clock divider`include "m320c50.inc"module m3s000ct (DI, READY, NRS, NCLKI, MPNMC, NBIO, NHOLD, NBRI,//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //    NNMI, NINT1, NINT2, NINT3, NINT4,    B0D, B1D, B2D, PD, SD, SRdy, PRdy, AI, RNWI, NSTRBI,    OA, IOD, OD, NDEN, NBR, NDS, NPS, NIS, NRD, NWR, XF, CLKO,    CLKXI, CLKR, TCLKXI, TCLKR,    DR, TDR, FSR, FSXI, TFSR, TFSXI,    CLKXO, NCLKXE, TCLKXO, NTCLKXE, TOUT, NIAQ, NHLDA, NHOE, IDLE2, NIACK,    DX, NDXE, TDX, NTDXE, FSXO, NFSXE, TFSXO, NTFSXE, TADD, NTADDE,    NBRD, NBWR, RA, WA, B0RA, B0WA,    PA, NPCE, NPWE, NPOE, SARA, SAWA, SAPA, SRNW, SPND, NSCE, NSWE, NSOE,    RNWO, NSTRBO);    input         READY, NRS, NCLKI, MPNMC, NBIO, NHOLD, NBRI;    input         NNMI, NINT1, NINT2, NINT3, NINT4;    input  [15:0] DI, PD, B0D, B1D, B2D, SD;    input  [14:0] AI;    input         PRdy, SRdy, RNWI, NSTRBI;    input         CLKXI, CLKR, TCLKXI, TCLKR;    input         DR, TDR, FSR, FSXI, TFSR, TFSXI;    output        XF, CLKO, CLKXO, NCLKXE, TCLKXO, NTCLKXE;    output        NIAQ, NHLDA, NHOE, IDLE2, NIACK, RNWO, NSTRBO;    output [14:0] PA, SARA, SAWA, SAPA;    output [8:0]  B0WA, B0RA, WA, RA;    output [2:0]  NBWR, NBRD;    output        NPCE, NPOE, NPWE;    output [15:0] OA, OD, IOD;    output [`C_NOSB-1:0] SRNW, SPND, NSCE, NSWE, NSOE;    output        NDEN, NPS, NDS, NIS, NWR, NRD, NBR;    output        DX, NDXE, TDX, NTDXE, FSXO, NFSXE, TFSXO, NTFSXE;    output        TADD, NTADDE, TOUT;    reg  [15:0] Intr;    wire        Reset, FClock, CLKO, ClockCPU, ClockPer, ClockInt, NHLDA, NHOE, NIAQ, IDLE2, NIACK;    wire        XF, HM, CLKXO, NCLKXE, TCLKXO, NTCLKXE, TOUT;    wire [15:0] PD, B0D, B1D, B2D, SD, DI;    wire [4:0]  PerIntr;    wire [8:0]  B0WA, B0RA, WA, RA;    wire [14:0] PA, SARA, SAWA, SAPA;    wire [15:0] OA, OD, IOD, PMMRWriteData, PMMRRdData;    wire [`C_NOSB-1:0]  SRNW, SPND, NSCE, NSWE, NSOE;    wire [6:0]  PMMRWrAddr, PMMRRdAddr;    wire [2:0]  NBWR, NBRD;    wire        NPCE, NPOE, NPWE;    wire        NPS, NDS, NIS, NWR, NRD, NDEN, NBR, InsFetch;    wire        ERdy, PMMRWr, PMMRRd, MemCycle;    wire        DX, NDXE, TDX, NTDXE, FSXO, NFSXE, TFSXO, NTFSXE;    wire        TADD, NTADDE, iIdle, iIdle2, ExtAccEnab, MemAccEnab, DMAMode, Wakeup;    wire        RNWO, NSTRBO, DWAccess, DRAccess, PAccess, IWAccess, IRAccess;    wire        NMIEdge, NInt1Edge, NInt2Edge, NInt3Edge, NInt4Edge;    wire  [2:0] DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo;    wire  [1:0] PAddr;// Clock and power-down controlm3s018ct U3 (NRS, NCLKI, NHOLD, HM, MemCycle, iIdle, iIdle2, NBRI, InsFetch,    Wakeup, NNMI, NINT1, NINT2, NINT3, NINT4,    Reset, FClock, CLKO, ClockCPU, ClockPer, ClockInt,    ExtAccEnab, MemAccEnab, DMAMode, NHLDA, NHOE, NIAQ, IDLE2,    NMIEdge, NInt1Edge, NInt2Edge, NInt3Edge, NInt4Edge);// Core interrupt assignmentsalways @(NInt1Edge or NInt2Edge or NInt3Edge or NInt4Edge or PerIntr)    Intr = {7'b0, NInt4Edge, PerIntr, NInt3Edge, NInt2Edge, NInt1Edge};// CPU Corem3s001ct U1 (FClock, ClockCPU, ClockInt, Reset, MPNMC, NBIO, NMIEdge, Intr,    DI, PD, B0D, B1D, B2D, SD, ERdy, PRdy, SRdy,    ExtAccEnab, MemAccEnab, DMAMode, MemCycle,    AI, RNWI, NSTRBI,    B0WA, B0RA, WA, RA, PA, SARA, SAWA, SAPA, NBWR, NBRD, NPCE, NPOE, NPWE,    SRNW, SPND, NSCE, NSWE, NSOE, OA, NPS, NDS, NIS, NWR, NRD,    IOD, OD, NDEN, NBR,    PMMRWrAddr, PMMRRdAddr, PMMRWriteData, PMMRRdData, PMMRWr, PMMRRd,    XF, HM, InsFetch,    iIdle, iIdle2, NIACK, RNWO, NSTRBO, Wakeup,    DWAccess, DRAccess, PAccess, IWAccess, IRAccess,    DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo, PAddr);// Peripheralsm3s020ct U2 (FClock, ClockCPU, ClockPer, Reset, PMMRWrAddr, PMMRRdAddr, PMMRWriteData,    PMMRRdData, PMMRWr, PMMRRd,    DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo, PAddr, READY, ERdy,    CLKXI, CLKR, TCLKXI, TCLKR, DR, TDR, FSR, FSXI, TFSR, TFSXI,    CLKXO, NCLKXE, TCLKXO, NTCLKXE, DWAccess, DRAccess, PAccess, IWAccess, IRAccess,    DX, NDXE, TDX, NTDXE, FSXO, NFSXE, TFSXO, NTFSXE, TADD, NTADDE, TOUT,    PerIntr);endmodule