module sys_TMS320C50 (NRS,NINT1,NINT2,NMI,NDS_O,NPS_O,NIS_O,NRD_O,NWR_O,NHOLDA,NIAQ,XF,NIACK,CLKOUT1,X1,TOUT,DX_O,TDX_O,TDO,A_O,D_O,RNW,NSTB,NBR_O,CLKX,TCLKX,TFSR,FSX,TFSX,CLK);input NRS,CLK,NINT1,NINT2,NMI;output NDS_O,NPS_O,NIS_O,NRD_O,NWR_O;output NHOLDA,NIAQ,XF,NIACK;output CLKOUT1,X1,TOUT,DX_O,TDX_O;output TDO;output [15:0] A_O,D_O;//inout [15:0] A,D;inout RNW,NSTB,NBR_O;inout CLKX,TCLKX;inout TFSR,FSX,TFSX;wire READY,NHOLD,NBIO,CLK;wire NINT1,NINT2,NINT3,NINT4;wire NMI,NRS,MPNMC;wire CLKMD1,CLKMD2;//unusewire CLKR,TCLKR,DR,TDR;wire CLKIN2;//unusewire FSR;wire TCK,TDI;//unusewire TMS,TRST,EMU0,EMU1;//unusewire NDS_O,NPS_O,NIS_O,NRD_O,NWR_O;wire NHOLDA,NIAQ,XF,NIACK;wire CLKOUT1,X1,TOUT,DX_O,TDX_O;wire TDO;wire [15:0] A,D;wire RNW,NSTB,NRB_O;wire CLKX,TCLKX;wire TFSR,FSX,TFSX;wire [15:0] A_O,D_O;//assign A_O = A;//assign D_O = D;assign READY = 1'b1;assign NHOLD = 1'b1;assign NBIO = 1'b1;//assign NINT1 = 1'b1;//assign NINT2 = 1'b1;assign NINT3 = 1'b1;assign NINT4 = 1'b1;//assign NMI = 1'b1;assign MPNMC = 1'b0;assign CLKMD1 = 1'b0;assign CLKMD2 = 1'b0;assign CLKR = 1'bz;assign TCLKR = 1'bz;assign DR = 1'bz;assign TDR = 1'bz;assign CLKIN2 = 1'b0;assign FSR = 1'bz;assign TCK = 1'b0;assign TDI = 1'b0;assign TMS = 1'b0;assign TRST = 1'b0;assign EMU0 = 1'b0;assign EMU1 = 1'b0;tms320c50_PLL U1 (READY,NHOLD,NBIO,NINT1,NINT2,NINT3,NINT4,NMI,NRS,MPNMC,CLKMD1,CLKMD2,CLKR,TCLKR,DR,TDR,CLKIN2,FSR,TCK,TDI,TMS,TRST,EMU0,EMU1,NDS_O,NPS_O,NIS_O,NRD_O,NWR_O,NHOLDA,NIAQ,XF,NIACK,CLKOUT1,X1,TOUT,DX_O,TDX_O,TDO,A,D,RNW,NSTB,NBR_O,CLKX,TCLKX,TFSR,FSX,TFSX,CLK);latch000 U2 (RNW,D,A,D_O,A_O);endmodule