//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //// Program Memory Controller// Copyright Mentor Graphics Corporation and Licensors 1998.// V1.101// Revision history// V1.101 - 19 November 1996//          Single address for program memory block (ProgAddr).//          Writes delayed by one cycle.// V1.100 - 22 October 1996//          PACntrl14 delayed by one cycle.// m3s013ct// M320C50 Internal program memory controller.// Provides address and control signals for the internal program memory.// The PrmRdy output is driven low if the PRdy input is low during a// read or write.module m3s013ct (ProgAddr, RdReq, WrReq, PRdy,//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //    MemCycle, FClock, Clock, Reset, MemAccEnab, PACntrl14,    PA, NPCE, NPOE, NPWE,    WriteReady, PrmRdy, PrWrRdy, PrProgValid);    input [14:0]  ProgAddr;    input         RdReq, WrReq, PRdy, WriteReady;    input         MemCycle, FClock, Clock, Reset, MemAccEnab, PACntrl14;    output [14:0] PA;    output        NPCE, NPOE, NPWE, PrmRdy, PrWrRdy, PrProgValid;    reg [14:0] PA, WrAddr;    reg  NPCE, NPOE, NPWE, PrmRead, PrmWrite, PrmRdy, RdCycRdy, RdConflict;    reg  RdCycle, WrCycle, RdActive, WrActive, PrWrRdy, PrProgValid;    reg  PACntrl14Del, WrReqDel;// Post write address and write requestalways @(posedge Clock)    if (MemCycle)    begin        WrAddr <= ProgAddr;        WrReqDel <= WrReq;    end// Select output address busalways @(WrActive or WrAddr or ProgAddr)    if (WrActive)        PA = WrAddr;    else        PA = ProgAddr;// Cycle controlleralways @(WrActive or RdReq or PRdy or RdConflict or WriteReady)begin    RdConflict = WrActive & RdReq;    RdCycRdy = ~(~PRdy | ~WriteReady | RdConflict);endalways @(posedge Clock or posedge Reset)    if (Reset)    begin        WrCycle <= 0;        RdCycle <= 0;    end    else    begin        WrCycle <= MemCycle | (WrCycle & ~PRdy);        RdCycle <= MemCycle | (RdCycle & ~RdCycRdy);    end// Access controlalways @(WrReqDel or WrCycle)    WrActive = WrReqDel & WrCycle;always @(RdReq or RdCycle or WrActive)    RdActive = RdReq & RdCycle & ~WrActive;// Ready signalalways @(RdReq or WrReqDel or RdConflict or PRdy)    PrmRdy = ~(((RdReq | WrReqDel) & ~PRdy) | RdConflict);// Write cycle ready signalalways @(WrActive or PRdy)    PrWrRdy = ~WrActive | PRdy;// Memory control signalsalways @(WrActive or RdActive or MemAccEnab)    NPCE = ~((WrActive | RdActive) & MemAccEnab);always @(posedge FClock or posedge Reset)    if (Reset)        NPOE <= 1;    else if (RdActive & (Clock | ~RdCycRdy) & MemAccEnab)        NPOE <= 0;    else        NPOE <= 1;always @(posedge FClock or posedge Reset)    if (Reset)        NPWE <= 1;    else if (WrActive & (Clock | ~PRdy) & MemAccEnab)        NPWE <= 0;    else        NPWE <= 1;// Delay PACntrl14always @(posedge Clock)   if (MemCycle)       PACntrl14Del <= PACntrl14;// Read program ready signalalways @(RdActive or WriteReady or PACntrl14Del)    PrProgValid = RdActive & (WriteReady | ~PACntrl14Del);endmodule