//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //// Conditional Branching and auxillary register control signals// Copyright Mentor Graphics Corporation and Licensors 1998.// V1.001// m3s046ct// M320C50 Conditional branch, call, return and execute.// and gating of decode signals with BCREnable.// InsRegHi = InstructReg[15:3]// ExRegLo  = ExecuteReg[9:0]// OpRegLo  = OpReg[9:0]module m3s046ct (NBIO, TC, AccNZ, AccLZ, C, OV,//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////These deliverables may be used for the purpose of making silicon for one  ////IC design only.  No further use of these deliverables for the purpose of  ////making silicon from an IC design is permitted without the payment of an   ////additional license fee.  See your license agreement with Mentor Graphics  ////for further details.  If you have further questions please contact        ////Mentor Graphics Customer Support.                                         ////                                                                          ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on         ////workstation hostid 800059c1 Inventra                                      //  InsRegHi, OpRegLo, OpReg11, ExRegLo, ExReg13, ExReg14, ExReg15,  OpCntrlReg0, OpCntrlReg1, OpCntrlReg2, OpCntrlReg6, OpCntrlReg7, OpCntrlReg8,  OpCntrlReg9, OpCntrlReg10, OpCntrlReg12, OpCntrlReg18, OpCntrlReg22,  ExCntrlReg2, ExCntrlReg3, ExCntrlReg5, ExCntrlReg7, ExCntrlReg8,  XCDel, BCRnD, IntrIns, ARZ, XCi, MMRins, IOins, RPTCZero, CycCntrlReg,  BCREnable, XCDis, IndCntrlReg);    input        NBIO, TC, AccNZ, AccLZ, C, OV;    input [12:0] InsRegHi;    input  [9:0] ExRegLo, OpRegLo;    input        OpReg11, ExReg13, ExReg14, ExReg15;    input        OpCntrlReg0, OpCntrlReg1, OpCntrlReg2, OpCntrlReg6;    input        OpCntrlReg7, OpCntrlReg8, OpCntrlReg9, OpCntrlReg10;    input        OpCntrlReg12, OpCntrlReg18, OpCntrlReg22;    input        ExCntrlReg2, ExCntrlReg3, ExCntrlReg5, ExCntrlReg7, ExCntrlReg8;    input        IntrIns, ARZ, XCi, BCRnD, XCDel;    input        MMRins, IOins, RPTCZero, CycCntrlReg;    output       BCREnable, XCDis;    output [8:0] IndCntrlReg;    reg       TPDis, AccCmpDis, ZLVCDis, BCRXCond, BCREnable;    reg       XCTPDis, XCACDis, XCZLVCDis, XCDis;    reg       BANZEnable, BCRnDDec, XCSkip, BCRSkip, EnableDec;    reg       MadMacOrTBLW, ModAR, EarlyWriteDec;    reg       iLARd, iLARi, FCycDec, IODec, ReadIndDec;    reg       LdARDec, LdARPDec, ARAUEnabDec, ARAUIpDec, ARAUrcDec;    reg       ARAUSubDec, ARAUCmpDec, ARAUImmDec, SARDec;    reg [8:0] IndCntrlReg;// BCR Conditionsalways @(NBIO or TC or AccNZ or AccLZ or C or OV or ExCntrlReg3  or ExRegLo or ExReg13 or ExReg14 or ExReg15)begin    TPDis = ((~ExRegLo[9] & ~ExRegLo[8] & NBIO) |            (~ExRegLo[9] & ExRegLo[8] & ~TC) |            (ExRegLo[9] & ~ExRegLo[8] & TC));    case (ExRegLo[3:2])        2'b00: AccCmpDis = 0;        2'b01: AccCmpDis = ~AccNZ | (ExRegLo[6] ^ AccLZ);        2'b10: AccCmpDis = (ExRegLo[7] ~^ AccNZ);        2'b11: if (ExRegLo[7]) AccCmpDis = AccNZ & (ExRegLo[6] ^ AccLZ);               else AccCmpDis = ~AccNZ | (ExRegLo[6] ^ AccLZ);    endcase    ZLVCDis = AccCmpDis | (ExRegLo[1] & (ExRegLo[5]^OV)) |         (ExRegLo[0] & (ExRegLo[4]^C));    BCRXCond = ~(TPDis | ZLVCDis);    BCREnable = ~(ExCntrlReg3 & (ExReg13 & ExReg14 & ExReg15) & ~BCRXCond);end// BCR Conditionsalways @(OpRegLo or NBIO or TC or AccNZ or AccLZ or C or OV or XCi)begin    XCTPDis = ((~OpRegLo[9] & ~OpRegLo[8] & NBIO) |               (~OpRegLo[9] & OpRegLo[8] & ~TC) |               (OpRegLo[9] & ~OpRegLo[8] & TC));    case (OpRegLo[3:2])        2'b00: XCACDis = 0;        2'b01: XCACDis = ~AccNZ | (OpRegLo[6] ^ AccLZ);        2'b10: XCACDis = (OpRegLo[7] ~^ AccNZ);        2'b11: if (OpRegLo[7]) XCACDis = AccNZ & (OpRegLo[6] ^ AccLZ);               else XCACDis = ~AccNZ | (OpRegLo[6] ^ AccLZ);    endcase    XCZLVCDis = XCACDis | (OpRegLo[1] & (OpRegLo[5]^OV)) |        (OpRegLo[0] & (OpRegLo[4]^C));    XCDis = XCi & (XCZLVCDis | XCTPDis);end// BANZ enablealways @(OpCntrlReg9 or OpReg11 or OpRegLo or ARZ)    BANZEnable = ~((OpCntrlReg9 & OpReg11 & OpRegLo[9] & OpRegLo[8]) & ARZ);// BCRnDDecalways @(OpCntrlReg0 or OpCntrlReg2 or OpCntrlReg6 or OpCntrlReg7 or  OpCntrlReg8 or OpCntrlReg9 or OpCntrlReg10 or OpCntrlReg12 or BANZEnable)    BCRnDDec = (OpCntrlReg2 | OpCntrlReg6 | OpCntrlReg7 | OpCntrlReg8 |         OpCntrlReg9 | OpCntrlReg10) & OpCntrlReg0 & ~OpCntrlReg12 & BANZEnable;// Conditional execute pipeline stuffingalways @(XCDel or XCDis or BCRnD or BCREnable)begin    XCSkip = XCDis | XCDel;    BCRSkip = BCRnD & BCREnable;end// Instruction decode enablealways @(ExCntrlReg2 or ExCntrlReg3 or ExCntrlReg5 or ExCntrlReg7 or ExCntrlReg8   or BCREnable or BCRnDDec or IntrIns or OpCntrlReg1 or XCSkip or BCRSkip)    EnableDec = ~((((ExCntrlReg3 & ~ExCntrlReg5) | ExCntrlReg2) &         ~(IntrIns & ~(ExCntrlReg8 | ExCntrlReg7)) & BCREnable) | BCRnDDec)         & OpCntrlReg1 & ~(XCSkip | BCRSkip);// MadMac or TBLW and AR modification instructionsalways @(InsRegHi)begin    MadMacOrTBLW = InsRegHi[12] & ~InsRegHi[11] & InsRegHi[10] & ~InsRegHi[9] &        ((~InsRegHi[7] & InsRegHi[6]) | (~InsRegHi[8] & InsRegHi[7] & InsRegHi[6] & InsRegHi[5]));    ModAR = (InsRegHi[12] & ~InsRegHi[11] & ~InsRegHi[10] & ~InsRegHi[9] & InsRegHi[8] & ~InsRegHi[7] &             InsRegHi[6] & InsRegHi[4]) |           (~InsRegHi[12] & InsRegHi[11] & InsRegHi[10] & InsRegHi[9] & InsRegHi[8] &            (InsRegHi[6] | InsRegHi[5]));end// Cycle control decodealways @(RPTCZero or CycCntrlReg or MMRins or IOins)    FCycDec = (MMRins | IOins) & ~CycCntrlReg & ~RPTCZero;// IODecalways @(InsRegHi)    IODec = ((!InsRegHi[12:9]) && InsRegHi[8] & InsRegHi[7] & ~InsRegHi[6] & ~InsRegHi[5])          | (InsRegHi[12] & ~InsRegHi[11] & InsRegHi[10] & ~InsRegHi[9] &             InsRegHi[8] & InsRegHi[7] & InsRegHi[6] & InsRegHi[5]);// EarlyWriteDecalways @(InsRegHi)   EarlyWriteDec = (~InsRegHi[12] & InsRegHi[11] & ~InsRegHi[10] & InsRegHi[9]                    & InsRegHi[8] & ~(InsRegHi[6] & InsRegHi[5]))                 | (~InsRegHi[12] & InsRegHi[11] & InsRegHi[10] & InsRegHi[9]                    & ~InsRegHi[8] & InsRegHi[6] &                     ((~InsRegHi[7] & ~InsRegHi[5]) | (InsRegHi[7] & InsRegHi[5])))                 | (InsRegHi[12] & ~InsRegHi[11] & ~InsRegHi[10] & ~InsRegHi[9]                    & (~InsRegHi[8] | (InsRegHi[8] &                      ((~InsRegHi[7] & ~InsRegHi[6] & ~InsRegHi[5]) | InsRegHi[7]))))                 | (InsRegHi[12] & ~InsRegHi[11] & ~InsRegHi[10] & InsRegHi[9])                 | (InsRegHi[12] & ~InsRegHi[11] & InsRegHi[10] & ~InsRegHi[9]                    & ((~InsRegHi[8] & (InsRegHi[7] | (InsRegHi[6] & InsRegHi[5])))                      | (InsRegHi[8] & ~(~InsRegHi[7] & InsRegHi[6] & ~InsRegHi[5]))));// LAR instructionsalways @(EnableDec or InsRegHi)begin    iLARd = (!InsRegHi[12:8]) & EnableDec;    iLARi = ((InsRegHi[12] & ~InsRegHi[11] & InsRegHi[10] & InsRegHi[9]) &       ((~InsRegHi[8]) | (InsRegHi[8] & InsRegHi[7] & InsRegHi[6] & InsRegHi[5]          & ~InsRegHi[4] & ~InsRegHi[3] & ~InsRegHi[2] & ~InsRegHi[1] & InsRegHi[0]))          & EnableDec);end// Indirect data read control decodealways @(InsRegHi or FCycDec or EnableDec or iLARd or iLARi or     OpCntrlReg18 or OpRegLo or ExCntrlReg8)begin    if (FCycDec)        ReadIndDec = ~iLARi &           ((iLARd & InsRegHi[4]) | (OpCntrlReg18 & OpRegLo[7]));    else    begin        if (EnableDec)            ReadIndDec = ((~InsRegHi[12] &                           (~InsRegHi[11] | ~InsRegHi[10] | ~InsRegHi[9] | ~InsRegHi[8])                & ~(~InsRegHi[11] & ~InsRegHi[10] & ~InsRegHi[9] & InsRegHi[8] & ~InsRegHi[6] &                   ((~InsRegHi[7] & InsRegHi[5]) | (InsRegHi[7] & ~InsRegHi[5]))))                | (InsRegHi[12] & ~InsRegHi[11] & InsRegHi[10] & ~InsRegHi[9]                   & ~InsRegHi[7] & InsRegHi[6]))                & InsRegHi[4];        else            ReadIndDec = 0;    endend// Indirect addressing control decodealways @(InsRegHi or ReadIndDec or EarlyWriteDec or EnableDec    or IODec or OpRegLo or MadMacOrTBLW or ModAR or XCSkip or BCRSkip    or OpCntrlReg1 or OpCntrlReg18 or OpCntrlReg22)begin    if (InsRegHi[12:1] == 12'hBF4) ARAUCmpDec = 1;    else ARAUCmpDec = 0;    if ((InsRegHi[12:9] == 4'h7) && (InsRegHi[8] & ~InsRegHi[6] & ~InsRegHi[5]))        ARAUImmDec = 1;    else ARAUImmDec = 0;    if (OpCntrlReg18 | OpCntrlReg22)    begin        ARAUSubDec = ~OpRegLo[5];        ARAUIpDec = OpRegLo[6];        ARAUrcDec = OpRegLo[6] & ~(OpRegLo[5]^OpRegLo[4]);    end    else    begin        if (ARAUImmDec)             ARAUSubDec = InsRegHi[7];        else ARAUSubDec = ~InsRegHi[2];        ARAUIpDec = InsRegHi[3] & ~(ARAUImmDec | ARAUCmpDec);        ARAUrcDec =  (InsRegHi[3] & ~(InsRegHi[2]^InsRegHi[1]) & ~(ARAUImmDec | ARAUCmpDec));    end    if (OpCntrlReg18 | OpCntrlReg22)    begin        LdARDec = OpRegLo[7];        LdARPDec = OpRegLo[7] & OpRegLo[3];        ARAUEnabDec = OpRegLo[7] & (OpRegLo[6] | OpRegLo[5] | OpRegLo[4]);        SARDec = 0;    end    else if (EnableDec & ~IODec)    begin        if (((ReadIndDec | ((EarlyWriteDec | MadMacOrTBLW) & InsRegHi[4]) |            ModAR) & (InsRegHi[3] | InsRegHi[2] | InsRegHi[1])) | ARAUImmDec)            LdARDec = 1;        else LdARDec = 0;        if (InsRegHi[0] && (InsRegHi[12:5] != 8'h0E) &&            (ReadIndDec | ((EarlyWriteDec | MadMacOrTBLW) & InsRegHi[4]) | ModAR))            LdARPDec = 1;        else LdARPDec = 0;        if ((LdARDec & (InsRegHi[3] | InsRegHi[2] | InsRegHi[1])) || ARAUImmDec)            ARAUEnabDec = 1;        else ARAUEnabDec = 0;        if (InsRegHi[12:8] == 5'b10000) SARDec = 1;        else SARDec = 0;    end    else    begin        LdARDec = 0;        LdARPDec = 0;        ARAUEnabDec = 0;        SARDec = 0;    end    IndCntrlReg = {SARDec,ARAUEnabDec,ARAUIpDec,ARAUrcDec,ARAUSubDec,                   ARAUImmDec,ARAUCmpDec,LdARPDec,LdARDec};endendmodule